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參數(shù)資料
| 型號(hào)： | M44C092 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁(yè)數(shù)： | 63/84頁(yè) |
| 文件大?。?/td> | 643K |
| 代理商： | M44C092 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
66 (84)
10111
00
11
0
11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Synchronize
Manchester demodulation mode
Timer 3
mode
T3EX
SI
SR–DATA
13817
T3I
CM31=SCI
10
011
0
Bit 0
Figure 77. Manchester demodulation
Combination mode 9: Biphase demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3
Timer 3 mode 11:
Biphase demodulation with Timer 3
In the Biphase demodulation mode the timer works like in the Manchester demodulation mode. The diffenence is that
the bits are decoded with the toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the
compare register 1 match event shifts the toggle flip-flop output into shift register. Before activating the demodulation
the timer and the demodulation stage must be synchronized with the bitstream. The Biphase code timing consists of
parts with the half bitlength and the complete bitlength. The synchronization routine must start the demodulator after
an interval with the complete bitlength.
The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode.
01
1
01
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Synchronize
Biphase demodulation mode
Timer 3
mode
T3EX
Q1=SI
CM31=SCI
SR–DATA
13818
00
0
T3I
Reset
Counter 3
10101
0
Bit 0
Figure 78. Biphase demodulation
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