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參數(shù)資料
| 型號： | M44C092 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 44/84頁 |
| 文件大小： | 643K |
| 代理商： | M44C092 |
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M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
49 (84)
Timer 3 Status Register 1 (T3ST) Read
Primary register address: ’C’hex – Read
Bit 3
Bit 2
Bit 1
Bit 0
T3ST
Read
– – –
T3ED
T3C2
T3C1
Reset value: x000b
T3ED
Timer 3 Edge Detect
This bit will be set by the edge-detect logic of Timer 3 input (T3I)
T3C2
Timer 3 Compare 2
This bit will be set when a match occurs between Counter 3 and T3CO2
T3C1
Timer 3 Compare 1
This bit will be set when a match occurs between Counter 3 and T3CO1
Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.
Timer 3 Clock Select Register (T3CS)
Address: ’B’hex – Subaddress: ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T3CS
T3E1
T3E0
T3CS1
T3CS0
Reset value: 1111b
T3E1
Timer 3 Edge select bit 1
T3E1
T3E0
Timer 3 Input Edge Select (T3I)
T3E0
Timer 3 Edge select bit 0
1
1
– – –
1
0
Positive edge at T3I pin
0
1
Negative edge at T3I pin
0
0
Each edge at T3I pin
T3CS1
Timer 3 Clock Source select bit 1
T3CS1
TCS0
Counter 3 Input Signal (CL3)
T3CS0
Timer 3 Clock Source select bit 0
1
1
System clock (SYSCL)
1
0
Output signal of Timer 2 (POUT)
0
1
Output signal of Timer 1 (T1OUT)
0
0
External input signal from T3I edge
detect
Timer 3 Compare- and Compare Mode Register
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the
content of the compare register with the current counter value. If both match, it generates a signal. This signal can be
used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for
the next counter stage. For each compare register an compare-mode register exists. This registers contain mask bits
to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a
compare match of the corresponding compare register. The mask bits for activating the single-action mode can also
be located in the compare mode registers. When assigned to the compare register a compare event will be supressed.
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