參數(shù)資料
型號： M37920F8CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 81/155頁
文件大小： 1274K
代理商： M37920F8CGP
31
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
ALE is an address latch enable signal. The latch is open while ALE =
“H”, so that an address signal passes through; the address is held
while ALE = “L”. After reset is removed, the function as pin ALE is
valid. By clearing the ALE output select bit of the processor mode
register 1 (address 5F16) to “0”, however, the ALE output is stopped
and this pin becomes programmable I/O port pin.
By setting the external bus wait number select bits of the processor
mode register 0 (address 5E16), the bus cycle wait number for the
external area or ALE expansion wait cycle can be selected (Note).
For details, refer to the section on the bus cycle.
HLDA is a hold request signal and is used to inform the external that
the microcomputer enters Hold state due to the acceptance of the
HOLD input.
HOLD is a hold request signal. It is an input signal used to make the
microcomputer enter Hold state. When this signal is at “L” level, a
Hold request is generated. The HOLD input is accepted after the
completion of the bus cycle during the BIU operation. In Hold state,
each of pins A0 to A23, D0 to D7, D8 to D15 (Pin BYTE’s level = “L”),
RD, BLW, BHW (Pin BYTE’s level = “H”), ALE, CS0 to CS3 enters the
floating state.
Hold state is terminated by changing the level at pin HOLD from “L”
to “H”. When Hold state is terminated, each floating state of the
above pins is terminated at the same timing that the level at pin
HLDA becomes “H”. Then, data access is started after 1 cycle of
φ1
is elapsed.
In Hold state, there is no restriction for access to the internal memory
area, and each of bus access and the CPU operates normally.
Therefore, microcomputer operates as far as software is assigned to
the internal memory area and data access is performed only to the
internal memory area.
When the external memory area is accessed, the microcomputer is
placed in the idling state until Hold state for that access is termi-
nated. Therefore, when software is assigned to the external memory
area, or when data access is performed to the external memory
area, the CPU stops its operation without execution of the next op-
eration.
After reset removal, functions as pins HOLD and HLDA are valid. By
clearing the HOLD input, HLDA output select bit of the processor
mode register 1 (address 5F16) to “0”, however, these functions be-
come invalid, and these pins become programmable I/O port pins.
Note that, once “0” is written to this bit after reset removal, this bit
cannot be back to “1” again.
RDY is a ready signal. The low-level period of the last
φ1 in the ac-
cess cycle for the external area will be extended when the level at pin
RDY becomes “L”. RDY is used to connect a external slow memory,
for example.
After reset removal, the function as pin RDY is valid. By clearing the
RDY input select bit of the processor mode register 1 (address 5F16)
to “0”, however, this bit functions as a programmable I/O port pin.
Note that, once “0” is written to this bit after reset removal, this bit
cannot be back to “1” again.
φ1 is the internal standard clock output pin. After reset removal, the
function as
φ1 output pin is selected. By clearing the clock φ1 output
select bit of the processor mode register 0 (address 5E16) to “0”,
however, this bit functions as a programmable I/O port pin.
The recovery cycle insert select bit of the processor mode register 1
(address 5F16) is used to insert an idling cycle equivalent to 1 bus
cycle. This prevents the new bus cycle occurrence for another exter-
nal area, just after the termination of the bus cycle for an external
area. This can be utilized for the bus arbitration on the external data
bus in the next bus cycle, for example, when connecting an external
memory of which data hold time is long.
After reset removal, the recovery cycle insertion is selected. By
clearing the recovery cycle insert select bit to “0”, however, the re-
covery cycle insertion is invalid (Note).
Note: The chip select wait controller, described later, is equipped
with the same function. This function is adopted to the area
out of the address area which is set by the chip select wait
controller.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37920FCCGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920FCCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920FGCGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920FGCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920S4CGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER
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