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參數(shù)資料
| 型號(hào)： | M37920F8CGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 140/155頁(yè) |
| 文件大小： | 1274K |
| 代理商： | M37920F8CGP |
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M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
DMA continuous transfer
(1) Single transfer mode
In the single transfer mode, only the preselected number of bytes are
transferred. As shown in Figure 69, first, set up the number of bits per
1 transfer unit, transfer method, transfer mode, and transfer address
direction by using the DMAi mode registers L and H. Then, write the
transfer source block’s first transfer address (the block’s lowest ad-
dress in the forward or fixed transfer address direction, or the block’s
highest address in the backward address direction) into the source
address register (hereinafter referred to as SAR). Further, write the
destination block’s first transfer address (the lowest address in the
forward or fixed transfer address direction, or the highest address in
the backward transfer address direction) into the destination address
register (hereinafter referred to as DAR). Also write the desired num-
ber of bytes to be transferred, into the transfer counter register (here-
inafter referred to as TCR). Write the value 1 or more into TCR. Each
of SAR, DAR, and TCR consists of 24 bits, therefore, be sure to write
into all these bits. The SAR, DAR, and TCR are located at the ad-
dresses shown in Figure 66. The next is to set a DMA source and
others by the DMAi control register shown in Figure 68. Set up bit 0
(priority select bit) and bit 1 (TC pin validity bit) of the DMAC control
register L shown in Figure 67, and finally set the DMAC control reg-
ister H’s DMA enable bit to “1” so as to make the DMA request ac-
ceptable.
When the contents of TCR are cleared to “0”, the terminal count sig-
nal (TC) is output, and at the same time, the interrupt request bit of
the DMA interrupt control register is set to “1”.
To forcedly terminate the DMA transfer, input “L” level to pin TC or
write the value “0” to the DMA enable bit. At this time, the interrupt
request bit of the DMA interrupt control register is not set to “1”.
Figure 78 shows a timing diagram example in the single transfer
mode on the following conditions:
Transfer unit: 16 bits
Transfer method: 2-bus cycle transfer
Transfer mode: Burst transfer mode (edge sense)
Transfer source address direction: Forward.
Transfer destination address direction: Forward.
Transfer source wait: 0 wait
Transfer destination wait: 0 wait
As 2-bus cycle transfer mode is selected, a read operation is per-
formed in the first bus cycle. First, the address written into the SAR
is output to the address bus and then inputted into the incrementor/
decrementor (hereinafter referred to as I/D). The I/D adds 1 or 2 to
the inputted address and outputs the result back to the SAR. If one
16-bit transfer operation is not enough to complete the read opera-
tion, the read operation is performed within 2 bus cycles to achieve
the purpose.
The operation is performed in the next bus cycle. First, the address
written in the DAR is output to the address bus and then inputted into
the I/D. The I/D adds 1 or 2 to the inputted address and outputs the
result back to the DAR. If one 16-bit transfer operation is not enough
to complete the write operation, the write operation is performed
within 2 bus cycles to achieve the purpose. The operation performed
so far is called the write cycle. The data stored in the BIU’s data latch
in the read cycle is output to the data bus in the write cycle and writ-
ten into the destination memory or external I/O. The operations per-
formed so far complete the transfer of 1 transfer unit. In the 2-bus
cycle transfer, the read and write cycle combination is called the
DMA transfer cycle. DMA transfer is executed by repeating the DMA
transfer cycle.
In the 2-bus cycle transfer, the TCR varies in the read cycle. The re-
maining transfer bytes are read from the TCR in concurrence with
address output from SAR in the read cycle and inputted into the
decrementor (hereinafter referred to as D). The D subtracts 1 or 2
from the number of remaining bytes and outputs the result back to
the TCR. In this manner, the contents of the TCR decrease each
time when 1-transfer-unit data has been transferred. When the num-
ber of remaining bytes, which was read from the TCR, becomes “0”,
the DMA controller outputs the terminal count signal (TC) to pin TC,
and at the same time, sets the interrupt request bit of the DMA inter-
rupt control register to “1”. At this time, the DMA enable bit is cleared
to “0”. As the burst transfer mode is selected in this example, the
DMA request bit is also cleared to “0”.
To forcedly terminate transfer, input “L” level to pin TC (P42) or write
the value “0” to the DMA enable bit.
In the single transfer, the first values written in the SAR, DAR, and
TCR are retained in the internal latches. Therefore, if DMA transfer
is to be performed under the same conditions, it can be initiated sim-
ply by setting the DMA enable bit to “1”.
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| M38039MFL-XXXWG | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PBGA64 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
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