- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67763 > M37920F8CGP 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | M37920F8CGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 30/155頁 |
| 文件大小： | 1274K |
| 代理商： | M37920F8CGP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁
125
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Function overview (CPU reprogramming mode)
The CPU reprogramming mode is available in the single-chip mode,
memory expansion mode, and boot mode to reprogram the user
ROM area only.
In the CPU reprogramming mode, the CPU erases, programs, and
reads the internal flash memory by writing software commands. Note
that the user-original reprogramming control software must be trans-
ferred to the internal RAM in advance to be executed.
The CPU reprogramming mode becomes active when “1” is written
into the flash memory control register ’s bit 1 (the CPU reprogram-
ming mode select bit) shown in Figure 120, and software commands
become acceptable.
In the CPU reprogramming mode, software commands and data are
all written to and read from even addresses (Note that address A0 in
byte addresses = “0”.) 16 bits at a time. Therefore, a software com-
mand consists of 8-bit units must be written only to an even address;
therefore, any data written to an odd address will be invalid.
The write state machine (WSM) in the flash memory controls the
erase and programming operations. What the status of the WSM
operation is and whether the programming or erase operation has
been completed normally or terminated by an error can be examined
by reading the status register.
Figure 120 shows the flash memory control register’s bit configura-
tion.
Bit 0 (the RY/BY status bit) is a read-only bit for indicating the WSM
operation. This bit goes to “0” (BUSY) while the automatic program-
ming/erase operation is active and goes to “1” (READY) during the
other operations.
Bit 1 serves as the CPU reprogramming mode select bit. Writing of
“1” to this bit selects the CPU reprogramming mode, and software
commands will be acceptable. Because the CPU cannot directly ac-
cess the internal flash memory in the CPU reprogramming mode,
writing to this bit 1 must be performed by the user-original repro-
gramming control software which has been transferred to the inter-
nal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and
“1” to this bit 1 successively. On the other hand, to clear this bit to “0”,
it is sufficient only to write “0”.
Bit 2 serves as the lock bit invalidity select bit, and setting this bit to
“1” invalidates the protection by a lock bit against erasing and pro-
gramming (block lock). The lock bit invalidity select bit can invali-
dates the lock bit function but set no lock bit itself. However, if erasing
is performed with this bit = “1”, a lock bit with value “0” (the locked
state) will be set to “1” (the unlocked state) after the erasing has
been completed. To set the lock bit invalidity select bit to “1”, write “0”
and “1” to this bit 2 successively with the CPU reprogramming mode
select bit = “1”. The manipulation of bit 2 is allowed only when the
CPU reprogramming mode select bit = “1”.
Bit 3 (the flash memory reset bit) resets the control circuit of the in-
ternal flash memory and is used when the CPU reprogramming
mode is terminated or when an abnormal access to the flash
memory happens. Writing of “1” to bit 3 with the CPU reprogramming
mode select bit = “1” preforms the reset operation. To remove the
reset, write “0” to bit 3 subsequently.
Bit 5 serves as the user ROM area select bit and is valid only in the
boot mode. Setting this bit to “1” in the boot mode switches an acces-
sible area from the boot ROM area to the user ROM area. To use the
CPU reprogramming mode in the boot mode, set this bit to “1”. Note
that when the microcomputer is booted up in the user ROM area,
only the user ROM area is accessible and bit 5 is invalid; on the other
hand, when the microcomputer is in the boot mode, bit 5 is valid in-
dependent of the CPU reprogramming mode. To rewrite bit 5, ex-
ecute the user-original reprogramming control software transferred
to the internal RAM in advance.
Figure 121 shows the CPU reprogramming mode set/termination
flowchart, and be sure to follow this flowchart. As shown in Note 1 of
Figure 121, before selecting the CPU reprogramming mode, set the
processor mode register 1’s bit 7 (the internal ROM bus cycle select
bit) to “0” and set flag I to “1” to avoid an interrupt request input.
When an NMI interrupt or a watchdog timer interrupt request is gen-
erated in the CPU reprogramming mode, when an input to the
RESET pin is “L”, or when the software reset is performed, the flash
memory control circuit and flash memory control register will be re-
set.
When the flash memory is reset during the erase or programming
operation, this operation is cancelled and the target block’s data will
be invalid. Just before writing a software command related to the
erase/programming operation, be sure to write to the watchdog
timer. Also, be sure to set the NMI pin to “H” to avoid an NMI interrupt
request occurrence.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38039MFL-XXXHP | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| M38039MFL-XXXSP | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PDIP64 |
| M38039MFL-XXXWG | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PBGA64 |
| M38039FFLHP | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| M38039FFLWG | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。