參數(shù)資料
型號(hào): M37920F8CGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 32/155頁
文件大?。?/td> 1274K
代理商: M37920F8CGP
127
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Table 26. Software commands (CPU reprogramming mode)
Command
Read Array
Read Status Register
Clear Status Register
Page Programming (Note 3)
Block Erase
Erase All Unclocked Block
Lock Bit Programming
Read Lock Bit Status
Address
X (Note 2)
X
FF16
7016
5016
4116
2016
A716
7716
7116
1st cycle
2nd cycle
Notes 1: At software commands’ input, the high-order byte of data (D8–D15) is ignored.
2: X = An arbitrary address in the user ROM area. (Note that A0 = “0”.)
3: SRD = Status register data.
4: WA = Write address, WD = Write data (16 bits).
WA and WD must be set from “0016” to “FE16”. (Byte addresses. Incremented by +2. Address A0 = “0”.) Page size = 128 words (128 ! 16 bits).
5: Block address: the maximum address of each block must be input. Note that address A0 = “0”.
6: D6 indicates the block lock status.
“1” = unlocked. “0” = locked.
Mode
Write
3rd cycle
(D0 to D7)
Data
Address
X
WA0 (Note 4)
BA (Note 5)
X
BA
SRD (Note 3)
WD0 (Note 4)
D016
D6 (Note 6)
Mode
Read
Write
Read
Data
Address
WA1
Mode
Write
The RY/BY status bit of the flash memory control register goes “0”
during the automatic programming operation; and also, it goes “1” af-
ter the end of it, the same way as bit 7 of the status register.
Reading out the status register after the automatic programming op-
eration is completed reports the result of it. For details, refer to the
section on the status register.
Figure 122 shows an example of the page programming flowchart.
Note that each block can be protected from programming by using a
lock bit. For details, refer to the section on the data protect function.
Additional programming to any page that has already been pro-
grammed is prohibited.
Block Erase Command (2016/D016)
Writing command code "2016" at the 1st bus cycle and writing verify
command code "D016" and the maximum address of the block (Note
that address A0 = “0”.) at the subsequent 2nd bus cycle initiate the
automatic erase (erasing and erase verification) operation for the
specified block.
The completion of the automatic erase operation is verified by a read
of the status register or a read of the flash memory control register.
As the automatic erase operation starts, the microcomputer enters
the read status register mode automatically to allow reading out the
contents of the status register. Bit 7 of the status register (SR.7) is
cleared to “0” simultaneously with the start of the automatic erase
operation; and also, it returns to “1” by the end of it. The read status
register mode is maintained until writing of the read array command
(FF16), writing of the read lock bit status command (7116), or per-
forming the reset operation with the flash memory reset bit.
___
The RY/BY status bit of the flash memory control register goes “0”
during the automatic erase operation; and also, it goes “1” after the
end of it, the same way as bit 7 of the status register.
Reading out the status register after the automatic erase operation
is completed reports the result of it. For details, refer to the section
on the status register.
Figure 123 shows an example of the block erase flowchart.
Note that each block can be protected from erasing by using a lock
Data
WD1
bit. For details, refer to the section on the data protect function.
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