
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
Zero page indirect absolute addressing mode
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Symbol
Contents
Symbol
Contents
+
–
/
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
V
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : The number of cycles “n” is increased by 1 when branching to the same page has occurred. The number of cycles “n” is increased by 2 when
branching to the other page has occurred.
6 : The number of cycles “n” is increased by 1 when branching to the other page has occurred.
7 : V flag is invalid in decimal operation mode.
8 : When this instruction is executed immediately after executing DEX, DEY, INX, INY, TAX, TSX, TXA, TYA, DEC, INC, ASL, LSR, ROL, or ROR
instructions, the number of cycles “n” becomes “3”. Furthermore, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when
branching to the same page has occurred. The number of cycles “n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page
has occurred.
9 : When this instruction is executed immediately after executing ASL, LSR, ROL, or ROR instructions, the number of cycles “n” becomes “3”. Further-
more, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when branching to the same page has occurred. The number of cycles
“n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page has occurred.
7641 Group
APPENDIX
3.7 Machine instructions
Rev.2.00
Aug 28, 2006
page 104 of 108
REJ09B0336-0200