
Rev.2.00
Aug 28, 2006
page 34 of 108
7641 Group
REJ09B0336-0200
APPENDIX
3.3 Notes on use
(5) Registers and bits
When using the endpoint 0, use the USB endpoint 0 IN max. packet size register for transmission
and reception (IN packet size and OUT packet size).
When not using the USB endpoint x (x = 0 to 4) IN max. packet size register and USB endpoint x
OUT max. packet size register, set them to “0”.
To write to/read from the USB interrupt status registers 1 and 2, perform it for the USB interrupt
status register 1 first and then the register 2.
To read from the USB endpoint x (x = 0 to 4) OUT write count registers Low and High, the lower
byte must be read first, then the higher byte.
Make sure the index indicated by the USB endpoint index register is correct when accessing the
registers: USB endpoint x (x = 0 to 4) IN control register, USB endpoint x OUT control register, USB
endpoint x IN max. packet size register, USB endpoint x OUT max. packet size register, USB
endpoint x (x = 0 to 4) OUT write count registers Low and High, USB endpoint FIFO mode register.
When the USB reset interrupt status flag is kept at “1”, all other flags in the USB internal registers
(addresses 005016 to 005F16) will return to their reset status. However, the following registers are
not affected by the USB reset: USB control register (address 001316), Frequency synthesizer control
register (address 006C16), Clock control register (address 001F16), and USB endpoint x FIFO register
(addresses 006016 to 006416).
When not using the USB function, set the USB line driver supply enable bit of the USB control
register (address 001316) to “1” for power supply to the internal circuits (at Vcc = 5 V).
The IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function.
Do not write to USB-related registers (addresses 005016 to 006416) except the USBC, CCR and FSC
until the USB clock is enabled.
When the MCU is in the USB-suspend state, the USB enable bit is kept “1”; the USB block is
enabled. To write to USB-related registers (addresses 005016 to 006416) except the USBC, CCR
and FSC after returning from the USB-suspend state; after enabling the USB clock, wait for 4 or
more
φ cycles and then set those registers.
When using the MCU at Vcc = 3.3V, set the USB line driver supply enable bit to “0” (line driver
disable). Note that setting the USB line driver current control bit (USBC3) doesn’t affect the USB
operation.
Setting the FLUSH bit to “1” eliminates the data in IN FIFO and OUT FIFO. If there are 2 or more-
data packets in them, the oldest data is eliminated. The FLUSH bit setting also affects the IN_PKT_RDY
bit or the OUT_PKT_RDY flag.
If the FLUSH bit is set to “1” while transmission/reception is being performed, the data might be
corrupted. When receiving, setting the FLUSH bit must be done while the OUT_PKT_RDY flag is
“1”. When transmitting in the isochronous transfer mode, use the AUTO_FLUSH function.
Use the AUTO_FLUSH bit (bit 6 of address 5816) in the double buffer mode.