
Rev.2.00
Aug 28, 2006
page 37 of 108
7641 Group
REJ09B0336-0200
APPENDIX
3.3 Notes on use
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(3) RD, WR pins
In the memory expansion mode or microprocessor mode, a read-out control signal is output from the
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RD pin (P36), and a write-in control signal is output from the WR pin (P37). “L” level is output from
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the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal
access and external access.
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(4) HLDA pin
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In spite of enabling the Hold function, the HLDA pin does not function when IBF1 output is enabled
in the master CPU bus interface.
(5) RDY function
When using RDY function in usual connection, it does not operate at 12 MHz of
φ or faster.
[Reason]
td(
φ-AH) + tsu(RDY-φ) = 31 ns (max.) + 21 ns (min.) = 52 ns.
twh (
φ), twl (φ) = 0.5 83.33 – 5 = 36.665 ns
Therefore, it becomes 52 ns > 36.665 ns, so that the timing to enter RDY wait does not match.
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However, if the timings can match owing to RDY pin by “L” fixation and others, the RDY function can
be used even at
φ = 12 MHz. In this situation the slow memory wait always functions.
(6) Wait function
The Wait function is serviceable at accessing an external memory in the memory expansion mode
and microprocessor mode. However, in these modes even if an external memory is assigned to
addresses 000816 to 000F16, the Wait function cannot function to these areas.
(7) Processor mode switch
Note when the processor mode is switched by setting of the processor mode bits (b1, b0 of CPMA),
that will immediately switch the accessible memory from external to internal or from internal to
external. If this is done, the first cycle of the next instruction will be operated from the accidental
memory.
To prevent this problem, follow the procedure below:
(a) Duplicate the next instruction at the same address both in internal and external memories.
(b) Switch from single-chip mode to memory expansion mode, jump to external memory, and then
switch from memory expansion mode to microprocessor mode. (Because in general, the problem
will not occur when switching the modes as long as the same memory is accessed after the
switch.
(c) Load a simple program in RAM that switches the modes, jump to RAM and execute the program,
then jump to the location of the code to run after the processor mode has switched.