![](http://datasheet.mmic.net.cn/90000/M37641M8-XXXHP_datasheet_3496247/M37641M8-XXXHP_317.png)
Rev.2.00
Aug 28, 2006
page 38 of 108
7641 Group
REJ09B0336-0200
APPENDIX
3.3 Notes on use
3.3.9 Notes on timer
(1) Read/Write for timer
The timer division ratio is : 1 / (n + 1)
(n = “0” to “255” written into the timer)
Read and write operation on 16-bit timer (Timers X and Y) must be performed for both high and low-
order bytes.
When reading the 16-bit timer (Timers X and Y), read the high-order byte first and then the low-order
byte. When writing to the 16-bit timer, write the low-order byte first and then the high-order byte.
Do not read the 16-bit timer during the write operation, or do not write to
it during the read
operation.
When the value is loaded only in the latch, the value is loaded in the timer at the count pulse
following the count where the timer reaches “0016”.
In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values of
reload latches. However, that may make count operation started. Therefore, write values again in
the order of timers 1, 2 and then timer 3 after their count sources have been switched.
In the timer mode (for timers X, Y, 1 to 3), event counter mode (for timers X, Y), pulse output mode
(for timers X, Y, 1, 2), the timer current count value can be read out by reading the timer.
In the pulse width measurement mode (for timer X), period measurement mode (for timer Y), pulse
width HL continuously measurement mode (for timer Y), the measured timer value is stored into the
internal temporary register. When reading the timer, the value of internal temporary register is read
out. The contents of internal temporary register is updated after the next measurement.
(2) Pulse output
When using the pulse output mode of timer X, set bit 3 of port P4 direction register to “1” (output
mode).
When using the TYOUT output of timer Y, set bit 4 of port P4 direction register to “1” (output mode).
When using the TOUT output of timer 1 or timer 2, set bit 1 of port P5 direction register to “1” (output
mode).
The TOUT output pin is shared with the XCOUT pin. Accordingly, when using f(XCIN)/2 as the timer 1
count source (bit 2 of timer 123 mode register = “0”), XCOUT oscillation drive must be disabled (bit
5 of clock control register = “1”) to input clocks from the XCIN pin.
The P51/XCOUT/TOUT pin cannot function as an ordinary I/O port while XCIN-XCOUT is oscillating. When
XCIN-XCOUT oscillation is stopped or XCOUT oscillation drive is disabled, this can be used as the TOUT
output pin of timer 1 or 2.
(3) Pulse input
When using the timer X in the event counter or pulse width measurement mode, set bit 3 of port
P4 direction register to “0” (input mode).
When using the timer Y in the period measurement, event counter or pulse width HL continuously
measurement mode, set bit 4 of port P4 direction register to “0” (input mode).
(4) Interrupt
In the timer Y’s pulse width HL continuously measurement mode, CNTR1 interrupt request is generated
at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active
edge switch bit of timer Y mode register.
(5) At STP instruction executed
When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal
clock
φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to
“0116” and the timer 1’s output is automatically selected as its count source. When the STP instruction
is being executed, all bits except bit 4 of the timer 123 mode register (address 002916) are initialized
to “0”. It is not necessary to set T123M1 (timer 1 count stop bit) to “0” before executing the STP