參數(shù)資料
型號(hào)： M37640E8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 82/96頁
文件大小： 1477K
代理商： M37640E8FP
83
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.4 TIMING REQUIREMENTS AND SWITCHING CHARACTERISCTICS
Table 2.4 Timing Requirements and Switching Characterisctics
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min
Typ. Max
Inputs
tw(RESET)
RESET input “Low” pulse width
2
_s
tc(Xin)
Clock input cycle time
41.66
ns
twh(Xin)
Clock input “High” pulse width
0.4*tc(Xin)ns
twl(Xin)
Clock input “Low” pulse width
0.4*tc(Xin)ns
tc(XCin)
Clock input cycle time
200
ns
twh(XCin)
Clock input “High” pulse width
0.4*tc(XCin)ns
twl(XCin)
Clock input “Low” pulse width
0.4*tc(XCin)ns
Interrupts
tc(INT)
INT0, INT1 input cycle time
200
ns
twh(INT)
INT0, INT1 input “High” pulse width
90
ns
twl(INT)
INT0, INT1 input “Low” pulse width
90
ns
tc(CNTRI)
CNTR0, CNTR1 input cycle time
200
ns
twh(CNTRI)
CNTR0, CNTR1 input “High” pulse width
80
ns
twl(CNTRI)
CNTR0, CNTR1 input “Low” pulse width
80
ns
Timers
td(
Φ-TOUT)
TIMER TOUT delay time (Note)
15
ns
td(
Φ-CNTR0)
TIMER CNTR0 delay time (pulse output mode) (Note)
15
ns
tc(CNTRE0)
TIMER CNTR0 input cycle time (event counter mode)
200
ns
twh(CNTRE0)
TIMER CNTR0 input “High” pulse width (event counter mode)
0.4*tc(CNTRE0)
ns
twl(CNTRE0)
TIMER CNTR0 input “Low” pulse width (event counter mode)
0.4*tc(CNTRE0)
ns
td(
Φ-CNTR1)
TIMER CNTR1 delay time (pulse output mode) (Note)
15
ns
tc(CNTRE1)
TIMER CNTR1 input cycle time (event counter mode)
200
ns
twh(CNTRE1)
TIMER CNTR1 input “High” pulse width (event counter mode)
0.4*tc(CNTRE1)
ns
twl(CNTRE1)
TIMER CNTR1 input “Low” pulse width (event counter mode)
0.4*tc(CNTRE1)
ns
SIO
tc(SCLKE)
SIO external clock input cycle time
400
ns
twh(SCLKE)
SIO external clock input “High” pulse width
190
ns
twl(SCLKE)
SIO external clock input “Low” pulse width
180
ns
tsu(SRXD-SCLKE)
SIO receive setup time (external clock)
15
ns
th(SCLKE-SRXD)
SIO receive hold time (external clock)
10
ns
td(SCLKE-STXD)
SIO transmit delay time (external clock)
25
ns
tv(SCLKE-SRDY)
SIO SRDY valid time (external clock)
26
ns
tc(SCLKI)
SIO internal clock output cycle time
166.66
ns
twh(SCLKI)
SIO internal clock output “High” pulse width
0.5*tc(SCLKI)-5
ns
twl(SCLKI)
SIO internal clock output “Low” pulse width
0.5*tc(SCLKI)-5
ns
tsu(SRXD-SCLKI)
SIO receive setup time (internal clock)
20
ns
th(SCLKI-SRXD)
SIO receive hold time (internal clock)
5
ns
td(SCLKI-STXD)
SIO transmit delay time (internal clock)
5
ns
_____
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