參數(shù)資料
型號： M37640E8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 32/96頁
文件大小： 1477K
代理商： M37640E8FP
38
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.1 SIO Control Registers (SIOCON)
The Serial I/O Control Register 1 controls various SIO
functions such as transfer direction and transfer clock
divisor (see Figure 1.37). All of this register’s bits can
be read from and written to by software. At reset, this
register is cleared to 0016.
SIO Control Register 2 determines the transfer clock
phase and polarity, and also whether the SIO is to
function in SPI compatible mode (see Figure 1.38). All
of this register’s bits can be read from and written to
by software. At reset, this register is set to 1816.
Fig. 1.38. SIO Control Register 2 (SIOCON2)
Fig. 1.37. SIO Control Register 1 (SIOCON1)
ISCSel0-2
Internal Synchronization Clock Select Bit (bits 2,1,0)
Bit 2
Bit 1
Bit 0
0
0 : Internal Clock Divided by 2
0
1 : Internal Clock Divided by 4
0
1
0 : Internal Clock Divided by 8
0
1
1 : Internal Clock Divided by 16
1
0
0 : Internal Clock Divided by 32
1
0
1 : Internal Clock Divided by 64
1
0 : Internal Clock Divided by 128
1
1 : Internal Clock Divided by 256
PSel
SIO Port Selection Bit (bit 3)
0 : I/O Port
1 : TxD output, SCLK function
RDYSel
SRDY Output Select Bit (bit 4)
0 : I/O Port
1 : SRDY signal
TDSel
Transfer Direction Select Bit (bit 5)
0 : LSB first
1 : MSB first
SCSel
Synchronization Clock Select Bit (bit 6)
0 : External Clock
1 : Internal Clock
OCHCont
TxD Output Channel Bit (bit 7)
0 : CMOS output
1 : N-Channel open drain output
OCHCont
TDSel
RDYSel
PSel
ISCSel2 ISCSel1 ISCSel0
MSB
7
LSB
0
Address: 002B
16
Access: R/W
Reset: 40
16
SCSel
S P I
SPI Mode Selection Bit (bit 0)
0 : Normal SIO mode
1 : SPI compatibe mode
CLKSEL
SIO Internal Clock Selection Bit (bit 1)
0:
.
1 : SCSGCLK
RXDSel
SRXD Input Selection Bit (bit 2)
0 : SRXD input disabled
1 : SRXD input enabled
CPol
Clock Polarity Selection Bit (bit 3)
0 : Clock is low between transfers
1 : Clock is high between transfers
CPHa
Clock Phase Selection Bit (bit 4)
0 : Data is captured on the leading edge of serial clock, changes
on the following edge.
1 : Data changes on the leading edge of serial clock, captured on
the following edge.
Bit 5-7
Reserved (Read/Write “0”)
Reserved
CPha
CPol
RXDSel CLKSEL
SP1
MSB
7
LSB
0
Address: 002C
16
Access: R/W
Reset: 18
16
Reserved
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