參數(shù)資料
型號: M34502M2-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù): 63/96頁
文件大?。?/td> 958K
代理商: M34502M2-XXXFP
66
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.22.1 Data Bus Buffer Status Registers
(DBBS0, DBBS1)
The data bus buffer status register is an 8-bit register
that indicates the data bus status, with bits 0, 1, and 3
being dedicated read-only bits. Bits 2, 4, 5, 6, and 7
are user definable flags set by software, and can be
read and write. When the A0 pin is high, the master
CPU can read the contents of this register. See Fig-
ures 1.77 to 1.80.
Output Buffer Full Flag (OBF0, OBF1)
The OBF0 and the OBF1 flags are set high when data
is written to the output data bus buffer by the slave
CPU and is cleared to “0” when data is read by the
master CPU.
Input Buffer Full Flag (IBF0, IBF1)
The IBF0 and the IBF1 flags are set high when data is
written to the input data bus buffer by the master CPU
and is cleared to “0” when data is read by the slave
CPU.
A0 Flag (A00, A01)
The level of the A0 pin is latched when data has been
written from the host CPU to the input data bus buffer.
1.22.2 Input Data Bus Buffer Registers
(DBBIN0, DBBIN1)
The data on the data bus is latched into DBBIN0 or
DBBIN1 by a write request from the master CPU. The
data in DBBIN0 or DBBIN1 can be read from the data
bus buffer register in the SFR area.
1.22.3 Output Data Bus Buffer Registers
(DBBOUT0, DBBOUT1)
Data is set in DBBOUT0 or DBBOUT1 by writing to
the data bus buffer register in the SFR area. When
the A0 pin is low, the data of this register is output by
a read request from the host CPU.
Fig. 1.77. Data Bus Buffer Status Register 0 (DBBS0)
Fig. 1.78. Data Bus Buffer Control Register 0 (DBBC0)
DBBC07
Reser ved
DBBC04
DBBC03
DBBCO2
DBBC01
DBBC00
MSB
7
LSB
0
Address: 004A
16
Access: R/W
Reset: 00
16
DBBC06
DBBC00
OBF Output Selection Bit (bit 0)
0: P5
2 pin is
operated as GPIO
1: P5
2 pin is
operated as OBF
0
output pin
DBBC01
IBF Output Selection Bit (bit 1)
0: P5
3 pin is
operated as GPIO
1: P5
3 pin is operated as IBF0
output pin
DBBC02
IBF
0 Inter r upt Selection Bit (bit 2)
0 : IBF
0 interrupt is generated by both write-data (A0= “0”) and write-
command (A
0 = “1”)
1 : IBF
0 interr upt is generated by write-command (A0 = “1”) only
DBBC03
Output buffer 0 empty interrupt disable Bit (bit 3)
0 : Enabled
1 : Disabled
DBBC04
Input buffer 0 full interrupt disable Bit (bit 4)
0 : Enabled
1 : Disabled
DBBC05
Reserved (Read/Write “0”)
DBBC06
Master CPU Bus Interface Enable Bit (bit 6)
0: P6
0-P6 7, P54-P57 are GPIO pins
1: P6
0-P6 7, P54-P57 are bus interface signals DQ0-DQ7, S 0, A0,
R,W respectively
DBBC07
Bus Interface Type Selection Bit (bit 7)
0 : RD, WR separate type bus
1 : R/W type bus.
DBBS07
DBBS05
DBBS04
DBBS03
DBBSO2
DBBS01
DBBS00
MSB
7
LSB
0
Address: 0049
16
Access: R/W
Reset: 00
16
DBBS06
DBBS00
Output Buffer Full (OBF
0) Flag (bit 0)
0 : Output buffer emopty.
1 : Output buffer full.
DBBS01
Input Buffer Full (BF0) Flag (bit 1)
0 : Input buffer empty.
1 : Input buffer full.
DBBS02
User Definable (U2) Flag (bit 2)
DBBS03
A
0(A00) Flag (bit 3)
Indicates the A
0 status when IBF flag is set
DBBS04
User Definable (U4) Flag (bit 4)
DBBS05
User Definable (U5) Flag (bit 5)
DBBS06
User Definable (U6) Flag (bit 6)
DBBS07
User Definable (U7) Flag (bit 7)
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