參數(shù)資料
型號: M34502M2-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù): 62/96頁
文件大?。?/td> 958K
代理商: M34502M2-XXXFP
65
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Bus
In
p
u
tD
ata
B
u
sB
u
ffe
r0
Ou
tp
u
tDa
ta
B
u
sB
u
ff
er
0
U
7
U6
U5
U4
A
00
U2
IBF0
b7
b0
System Bus
OBF0
b1
b0
D
ata
B
u
s
Bu
ff
er
Co
n
tro
lRe
g
is
te
r0
OBF0 IBF0 A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
S0 R W
RD
WR
DBB
0
DBBS0
In
p
u
tD
ata
B
u
sB
u
ffe
r1
Ou
tp
u
tDa
ta
Bu
sBu
ff
er
1
U
7
U6
U5
U4
A
01
U2
IBF1
b7
b0
OBF1
b1
b0
D
ata
Bu
sB
u
ff
er
Co
n
tro
lRe
g
is
te
r
1
OBF1
IBF1
A0
S1
R
W
RD
WR
DBB
1
DBBS1
Fig. 1.75. Bus Interface Circuit
Fig. 1.76. Data Bus Buffer Interrupt Request Circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
Rising Edge
detection circuit
Rising Edge
detection circuit
Rising Edge
detection circuit
Rising Edge
detection circuit
Input Buffer full interrupt
request signal IBF
Output Buffer Empty interrupt
request signal OBE
Input buffer full flag 0
IBF0
Input buffer full flag 1
IBF1
Output buffer full flag 0
OBF0
Output buffer full flag 1
OBF1
Set interrupt request at this rising edge
IBF0
IBF1
IBF
OBF1
OBE
(OBE1)
OBF0
(OBE0)
1.22 MASTER CPU BUS INTERFACE
This device has a bus interface function with 2 I/O buff-
ers that can be operated in slave mode by control
signals from the master CPU (see Figure 1.75). Bus
Interface Circuit). The bus interface can be connected
directly to either a R/W type of CPU or a CPU with RD
and WR separate signals. Slave mode is selected
with the bit 7 of the data buffer control register 0. The
single data bus buffer mode and the double data bus
buffer mode are selected with bit 7 of the Data Bus
Buffer Control register 1. When selecting the double
data bus buffer mode, Port P72 becomes S1 input.
Prior to enabling the MBI, Port 6 must be placed in in-
put mode by writing 0016 to P6D (001516).
When data is written to the MCU from the master
CPU, an input buffer full interrupt request occurs.
Similarly, when data is read from the master CPU, an
output buffer empty interrupt request occurs.
When the bus interface is operating, DQ0-DQ7 be-
come a 3-state data bus that sends and receives
data, command, and status to and from the master
CPU. At the same time, W, R, S0, S1, and A0 become
host CPU control signal input pins.
The two input buffer full interrupt requests and two out-
put buffer full requests are multiplexed as shown in
Figure 1.76.
The bus interface can be operated under normal
MCU control or under on-chip DMA control for fast
data transfer. If a master CPU has a large amount of
data to be transferred, use of the on-chip DMA con-
troller is highly recommended.
The bus interface signal input level can be pro-
grammed as CMOS level (default) or as TTL level.
Bit7 of the Port Control Register (PTC7) is used for the
input level selection.
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