參數(shù)資料
型號： M34502M2-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 37/96頁
文件大小： 958K
代理商： M34502M2-XXXFP
42
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1.42. UART Mode Register (U1MOD, U2MOD)
Fig. 1.43. UART Control Register (U1CON, U2CON)
LE1
PEN
PMD
STB
PS1
PS0
CLK
MSB
7
LSB
0
Address: 0030
16 ,003816
Access: R/W
Reset: 00
16
LE0
1.19.1 UART Mode Register (UxMOD)
UxMOD defines data formats and selects the clock to
be used (see Figure 1.42).
1.19.2 UART Control Register (UxCON)
The UxCON specifies the initialization and enabling of a
transmit/receive process (see Figure 1.43). Data can
be read from and written to the Control Register.
CLK
UART Clock Selection Bit (bit 0)
0:
.
1: SCSGCLK
PS1,0
Internal Clock Prescaling Selection Bits (bits 2,1)
Bit 2
Bit 1
0
0: Division by 1
0
1: Division by 8
1
0: Division by 32
1
1: Division by 256
STB
Stop Bits Selection Bit (bit 3)
0: 1
1: 2
PMD
Parity Selection Bit (bit 4)
0: Even
1: Odd
PEN
Parity Enable Bit (bit 5)
0: Off
1: On
LE1,0
Uart Character Length Selection Bits (bits 7,6)
Bit 7
Bit 6
0
0: 7 bits/character
0
1: 8 bits/character
1
0: 9 bits/character
1
1: Reserved
A M E
CTS_SEL
TIS
RIN
TIN
REN
TEN
MSB
7
LSB
0
Address: 0033
16 ,003B16
Access: R/W
Reset: 00
16
RTS_SEL
TEN
Transmission Enable Bit (bit 0)
0: Disable the transmit process
1: Enable the transmit process. If the transmit process is disabled (TEN
cleared) during transmission, the transmit will not stop until completed.
REN
Receive Enable Bit (bit 1)
0: Disable the receive process
1: Enable the receive process. If the receive process is disabled (REN
cleared) during reception, the receive will not stop until completed.
TIN
Transmission Initialization Bit (bit 2)
0: No action
1: Resets the UART transmit status register bits as well as stopping the
transmission operation. The TEN bit must be set and the transmit
buffer reloaded in order to transmit again. The TIN is automatically
reset one cycle after Tin is set.
RIN
Receive Initialization Bit (bit 3)
0: No action
1: Clears the UART receive status flags and the REN bit. If RIN is set
during receive in progress, receive operation is aborted. The RIN bit
is automatically reset one cycle after RIN is set.
TIS
Transmit Interrupt Source Selection Bit (bit 4)
0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
1: Transmit interrupt occurs when the Transmit Complete flag is set.
CTS_SEL
Clear-to Send (CTS) Enable Bit (bit 5)
0: CTS function is disabled. P8
6 (or P82) is used as GPIO pin.
1: CTS function is enabled. P8
6 (or P82) is used as CTS input.
RTS_SEL
Request-to-Send (RTS) Enable Bit (bit 6)
0: RTS function is disabled, P8
7 (or P83) is used as GPIO pin.
1: RTS function is enabled, P8
7 (or p83) is used as RTS output.
AME
UART Address Mode Enable Bit (bit 7)
0: Address Mode disabled
1: Address Mode enabled
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