參數(shù)資料
型號(hào)： M34502M2-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 28/96頁(yè)
文件大?。?/td> 958K
代理商： M34502M2-XXXFP
34
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Each time the Timer Y underflows, the output of the
CNTR1 pin is inverted, and the corresponding Timer
Y interrupt request bit is set to a “1”. The repeated in-
version of the CNTR1 pin output produces a
rectangular waveform with a duty ratio of 50 percent.
The initial level of the output is determined by the
CNTR1 polarity select bit (bit 6). When this bit is low,
the output starts from a high level. When this bit is
high, the output starts from a low level.
Pulse Period Measurement Mode
Count Source:
F/n (where n is 8, 16, 32, or 64).
This mode measures the period of the event wave-
form input to the CNTR1 pin.
CNTR1 Polarity Select Bit (TYM6) = “0”
When the falling edge of an event waveform is de-
tected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is as-
signed
the
same
address
as
Timer
Y.
Simultaneously, the value in the Timer Y reload
latch is transferred to Timer Y, and Timer Y contin-
ues counting down. The falling edge of an event
waveform also causes the CNTR1 interrupt re-
quest; therefore, the period of the event waveform
from falling edge to falling edge is found by read-
ing Timer Y in the CNTR1 interrupt routine. The
data read from Timer Y is the data previously
stored in its temporary register.
CNTR1 Polarity Select Bit (TYM6) = “1”
When the rising edge of an event waveform is de-
tected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is as-
signed
the
same
address
as
Timer
Y.
Simultaneously, the value in the Timer Y reload
latch is transferred to Timer Y, and Timer Y contin-
ues counting down.
The rising edge of an event waveform also causes
the CNTR1 interrupt request; therefore, the period
of the event waveform from rising edge to rising
edge is found by reading Timer Y in the CNTR1 in-
terrupt routine. The data read from Timer Y is the
data previously stored in its temporary register.
Each time the timer underflows, the Timer Y interrupt
request bit is set to a “1”, the contents of the timer re-
load latch are loaded into the timer, and the
countdown sequence begins again.
Event Counter Mode
Count Source: CNTR1
Timer countdown is triggered by input to the CNTR1
pin. Each time a timer underflows, the correspond-
ing timer interrupt request bit is set to a “1”, the
contents of the timer reload latch are loaded into the
timer, and the countdown sequence begins again.
The edge used to clock Timer Y is determined by
the CNTR1 polarity select bit (bit 6). When these
bits are “0”s, the timers are clocked on the rising
edge. When these bits are “1”s, the timers are
clocked on the falling edge
HL Pulse-width Measurement Mode
Count Source:
F/n (where n is 8, 16, 32, or 64).
This mode continuously measures both the logical
high pulse width and the logical low pulse width of
an event waveform input to the CNTR1 pin. When
the falling (or rising) edge of the event waveform is
detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned
the same address as Timer Y, regardless of the set-
ting of the CNTR1 polarity select bit. Simultaneously,
the value in the Timer Y reload latch is transferred to
Timer Y, which continues counting down. The falling
or rising edge of an event waveform causes the
CNTR1 interrupt request; therefore, the width of the
event waveform from the falling or rising edge to ris-
ing or falling edge is found by reading Timer Y in the
CNTR1 interrupt routine. The data read from Timer Y
is the data previously stored in its temporary regis-
ter.
Each time the timer underflows, the Timer Y interrupt
request bit is set to a “1”, the contents of the timer
reload latch are loaded into the timer, and the count-
down sequence begins again.
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