參數(shù)資料
型號： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 86/159頁
文件大小： 3896K
代理商： M30833FJFP
Rev.3.00
2004.08.06
page 30 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(5) Notes on External 1 interrupt
Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in software, be careful about the following notes.
Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 3 of regis-
ter I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 21) and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
21).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 21).
LA
4
; ( 02)
TV1A
; The SNZ1 instruction is valid ...........
LA
8
; (12)
TI2A
; Control of INT1 pin input is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 21 External 1 interrupt program example-1
Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to “0” , the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
When the input of INT1 pin is disabled (register I23 = “0”), set the
key-on wakeup function to be invalid (register K22 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 22).
LA
0
; (02)
TK2A
; Input of INT1 key-on wakeup invalid ..
DI
EPOF
POF
; RAM back-up
: these bits are not used here.
Fig. 22 External 1 interrupt program example-2
Note on bit 2 of register I2
When the interrupt valid waveform of the P31/INT1 pin is
changed with the bit 2 of register I2 in software, be careful about
the following notes.
Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 2 of regis-
ter I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to
Figure 23) and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
23).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 23).
LA
4
; ( 02)
TV1A
; The SNZ1 instruction is valid ...........
LA
12
; (12)
TI2A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 23 External 1 interrupt program example-3
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