參數(shù)資料
型號: M30833FJFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 68/159頁
文件大小: 3896K
代理商: M30833FJFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Overview
15
Table 1.1.6. Pin Description (100-Pin and 144-Pin Packages) (Continued)
Function
I/O port P5
Bus control pin
UART pin
Description
I/O
O
I
O
I
O
I
I/O
I
I/O
O
I
I/O type
O
P50 to P57
CLKOUT
ISCLK
OUTC21
Symbol
Clock output
I/O port P6
Intelligent I/O pin
DRAM bus control pin
P60 to P67
I/O pins for UART0 (P60 to P63) and UART1 (P64 to P67)
Outputs a XIN divided by 8 or divided by 32 or a clock having the
same frequency as XCIN from P53.
WRL
WR
WRH
BHE
RD
BCLK
HLDA
HOLD
ALE
RDY
O
I/O
ISCLK2 inputs and outputs a clock for the intelligent I/O
communication function.
OUTC21 outputs a clock for the waveform generation function.
8-bit I/O ports equivalent to P0
I : Input
O : Output
I/O : Input and output
Output WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE
signals. WRL and WRH or BHE and WR can be switched by
program.
WRL, WRH, RD is selected
WRL signals is set to "L" when writing data to an even address in
external memory space.
WRH signal is set to "L" when writing data to an odd address in
external memory space.
RD shignal is set to "L" when reading data in extenal memory
space.
WR, BHE, RD is selected
WR signal is set to "L" when writing data in external memory
space.
RD signal is set to "L" when reading data in external memory
space.
BHE signal is set to "L" when accessing data to an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
While in an input level HOLD pin is set to "L", the microcomputer
is placed in a hold state.
In a hold state, HLDA outputs "L" level.
ALE latches the address.
While an input level of the RDY pin is set to "L", the
microcomputer is placed in a wait state.
DW
CASL
CASH
RAS
DW signal is set to "L" when writing data to DRAM space.
CASL and CASH signals indicate a timing to latch column
address.
CASL is set to "L" when accessing an even addess.
CASH is set to "L" when accessing an odd address.
RAS signal latches row address.
8-bit I/O ports equivalent to P0.
CTS0, CTS1
RTS0, RTS1
SS0, SS1
CLK0, CLK1
RxD0, RxD1
SCL0, SCL1
STxD0, STxD1
TxD0, TxD1
SDA0, SDA1
SRxD0, SRxD1
I/O
O
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