參數(shù)資料
型號(hào): M30833FJFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 15/159頁
文件大?。?/td> 3896K
代理商: M30833FJFP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.3.00
2004.08.06
page 109 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
TAD (Transfer data to Accumulator from register D)
0001010001
051
11
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation:
(A2–A0)
← (DR2–DR0)
(A3)
← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABSI (Transfer data to Accumulator and register B from register SI)
1001111000
278
11
Grouping:
Other operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
register SI to register B, and transfers the
low-order 4 bits (SI3–SI0) of register SI to
register A.
Operation:
(B)
← (SI7–SI4)
(A)
← (SI3–SI0)
TADAB (Transfer data to register AD from Accumulator from register B)
1000111001
239
11
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), this in-
struction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), trans-
fers the contents of register B to the
high-order 4 bits (AD7–AD4) of comparator
register, and the contents of register A to
the low-order 4 bits (AD3–AD0) of compara-
tor register.
(Q13 = bit 3 of A/D control register Q1)
Operation:
(AD7–AD4)
← (B)
(AD3–AD0)
← (A)
TAI1 (Transfer data to Accumulator from register I1)
1001010011
253
11
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
Operation:
(A)
← (I1)
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