參數(shù)資料
型號： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 112/159頁
文件大?。?/td> 3896K
代理商： M30833FJFP
Rev.3.00
2004.08.06
page 54 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 42 Structure of reset pin and its peripherals, and power-on reset operation
Name
D0–D5
D6/CNTR0
C/CNTR1
P00–P03
P10–P13
P20, P21, P22
P30/INT0, P31/INT1, P32, P33
P40–P43
P50–P53
P60/AIN0, P61/AIN1, P62, P63
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
Function
D0–D5
D6
C
P00–P03
P10–P13
P20–P22
P30–P33
P40–P43
P50–P53
P60–P63
State
High-impedance (Notes 1, 2)
“L” (VSS) level
High-impedance (Notes 1, 2, 3)
High-impedance (Note 1)
High-impedance (Notes 1, 2)
High-impedance (Note 1)
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V until the value of supply voltage reaches the minimum
operating voltage must be set to 100
s or less.
If the rising time exceeds 100
s, connect a capacitor between the
RESET pin and VSS at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
Table 14 Port state at reset
RESET pin
WE
SRST instruction
F
Watchdog reset signal
(Note 1)
Pull-up transistor
(Note 1)
Power-on reset circuit
Voltage drop detection circuit
VDD (Note 3)
100
∝s or less
(Note 2)
Internal reset signal
Power-on
Reset released
Internal reset signal
Reset
state
Notes 1:
This symbol represents a parasitic diode.
2:
Applied potential to RESET pin must be V
DD
or less.
3:
Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Power-on reset circuit output
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