參數(shù)資料
型號： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 115/159頁
文件大小： 3896K
代理商： M30833FJFP
Rev.3.00
2004.08.06
page 57 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
EPOF instruction +
POF instruction
Q
S
R
SVDE instruction
Internal reset signal
Key-on wakeup signal
Q
S
R
+
–
VRST
+
-
VDCE
Voltage drop detection circuit
Reset signal
Voltage drop detection circuit
VRST (reset release voltage)
+
-
VDD
Voltage drop detection circuit
Reset signal
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
VRST (reset voltage)
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
When the level of the VDCE pin is “H” and CPU is operating, the
voltage drop detection circuit is valid.
Fig. 45 Voltage drop detection reset circuit
Fig. 46 Voltage drop detection circuit operation waveform
Table 15 Voltage drop detection circuit operation state
VDCE pin
“L”
“H”
At CPU operating
Invalid
Valid
At RAM back-up
(SVDE instruction not executed)
Invalid
At RAM back-up
(SVDE instruction executed)
Invalid
Valid
(2) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 47);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
Fig. 47 VDD and VRST–
VDD
Recommended
operatng condition
min.value
No reset
Program failure may occur.
VRST
+
VRST
–
VDD
Recommended
operatng condition
min.value
VRST
+
VRST
–
→ Normal operation
Reset
(1) SVDE instruction
When the SVDE instruction is executed, the voltage drop detec-
tion circuit is valid even after system enters into the RAM
back-up mode. The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the
system reset is required.
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