參數資料
型號: M30833FJFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數: 126/159頁
文件大?。?/td> 3896K
代理商: M30833FJFP
Rev.3.00
2004.08.06
page 67 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accord-
ingly, be careful not to over the stack when performing these
operations together.
Multifunction
The input/output of P30 and P31 can be used even when INT0
and INT1 are selected.
The input/output of D6 can be used even when CNTR0 (input) is
selected.
The input of D6 can be used even when CNTR0 (output) is selected.
The “H” output of C can be used even when CNTR1 (output) is se-
lected.
10
11
12
Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
Timer count source
Stop timer 1, 2, 3 and 4 counting to change its count source.
Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
Writing to the timer
Stop timer 1, 2, 3 or 4 counting and then execute the data write
instruction (T1AB, T2AB, T3AB, T4AB) to write its data.
Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or re-
load regiser R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
Timer 4
Avoid a timing when timer 4 underflows to stop timer 4 at the use
of PWM output function..
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
Timer input/output pin
When the PWM signal is output from C/CNTR1 pin, set the out-
put latch of port C to “0”.
Watchdog timer
The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
The watchdog timer function is valid after system is returned from
the RAM back-up state. When not using the watchdog timer func-
tion, execute the DWDT instruction and the WRST instruction
continuously every system is returned from the RAM back-up
state, and stop the watchdog timer function.
When the watchdog timer function and RAM back-up function are
used at the same time, execute the WRST instruction before sys-
tem enters into the RAM back-up state and initialize the flag
WDF1.
LIST OF PRECAUTIONS
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
connect a bypass capacitor (approx. 0.1
F) between pins VDD
and VSS at the shortest distance,
equalize its wiring in width and length, and
use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 k
(connect this resistor to CNVSS/
VPP pin as close as possible).
Register initial values 1
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset,
set initial values.
Register Z (2 bits)
Register D (3 bits)
Register E (8 bits)
Register initial values 2
The initial value of the following registers are undefined at RAM back-
up. After system is returned from RAM back-up, set initial values.
Register Z (2 bits)
Register X (4 bits)
Register Y (4 bits)
Register D (3 bits)
Register E (8 bits)
13
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