參數(shù)資料
型號： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 76/159頁
文件大小： 3896K
代理商： M30833FJFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
22
Flag Register (FLG)
The flag register (FLG) is 16 bits long to show the CPU status.
(1) Carry Flag (C)
The C flag indicates carry and borrow status after an instruction is executed.
(2) Debug Flag (D)
The D flag is for debug only. It should be set to "0".
(3) Zero Flag (Z)
The Z flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise, set
to "0".
(4) Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise, set
to "0".
(5) Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
(6) Overflow Flag (O)
The O flag is set to "1" when an arithmetic operation overflows; otherwise, is set to "0".
(7) Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0" and is enabled when the I flag is set to "1". The I
flag is set to "0" when an interrupt is acknowledged.
(8) Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when the hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
(9) Processor Interrupt Priority Level (IPL)
IPL is 3 bits long to assign interrupt priority levels from level 0 to level 7.
If a requested interrupt has a greater priority than IPL, the interrupt is enabled.
(10) Reserved Space
When write, the reserved space should be set to "0". When read, its content is indeterminate.
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