參數(shù)資料
型號： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 134/159頁
文件大小： 3896K
代理商： M30833FJFP
Rev.3.00
2004.08.06
page 74 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
W21
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
Count source
System clock (STCK)
Prescaler output (ORCLK)
Timer 1 underflow signal (T1UDF)
PWM signal (PWMOUT)
CNTR0 output signal selection bit
Timer 2 control bit
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
Timer control register W2
at RAM back-up : state retained
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
W23
W22
W21
W20
MR3
Clock control register MR
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
On-chip oscillator clock (f(RING))
at reset : 11112
at RAM back-up : 11112
MR3
0
1
R/W
TAMR/
TMRA
Main clock f(XIN) oscillation circuit control bit
System clock oscillation source selection bit
Operation mode selection bits
0
1
0
1
MR2
0
1
0
1
MR1
MR0
MR2
0
1
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
On-chip oscillator (f(RING)) control bit
Clock control register RG
W
TRGA
at RAM back-up : 02
at reset : 02
RG0
W11
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
XIN input
CNTR0 input
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 1 control bit
Timer 1 count source selection bits
0
1
0
1
W10
0
1
0
1
Timer control register W1
R/W
TAW1/TW1A
at RAM back-up : state retained
at reset : 00002
W13
W12
W11
W10
R/W
TAW2/TW2A
0
1
Stop (state initialized)
Operating
Prescaler control bit
Timer control register PA
W
TPAA
at RAM back-up : 02
at reset : 02
PA0
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