參數(shù)資料
型號(hào)： M30833FJFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 131/159頁
文件大小： 3896K
代理商： M30833FJFP
Rev.3.00
2004.08.06
page 71 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
POF instruction
When the POF instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF instruction.
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction and the POF instruction
continuously.
Program counter
Make sure that the PC does not specify after the last page of the
built-in ROM.
Power-on reset
When the built-in power-on reset circuit is used, the time for the
supply voltage to rise from 0 V to the value of supply voltage or
more must be set to 100
s or less. If the rising time exceeds 100
s, connect a capacitor between the RESET pin and VSS at the
shortest distance, and input “L” level to RESET pin until the value
of supply voltage reaches the minimum operating voltage.
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 68);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
19
21
A/D converter-1
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “ 0”
to change the operating mode of
the A/D converter from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
LA
8
; (02)
TV2A
; The SNZAD instruction is valid ........
LA
0
; (02)
TQ1A
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
SNZAD
NOP
: these bits are not used here.
Fig. 65 A/D converter program example-3
Fig. 66 Analog input external circuit example-1
A/D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog volt-
age is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may
not be obtained. Therefore, reduce the impedance or, connect a
capacitor (0.01
F to 1 F) to analog input pins (Figure 66).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 67. In addition, test
the application products sufficiently.
17
18
Fig. 67 Analog input external circuit example-2
20
Fig. 68 VDD and VRST–
VDD
Recommended
operatng condition
min.value
No reset
Program failure may occur.
VRST
+
VRST
–
VDD
Recommended
operatng condition
min.value
VRST
+
VRST
–
→ Normal operation
Reset
22
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Sensor
AIN
About 1k
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