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參數資料
| 型號： | M306V5EESP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, PLASTIC, SDIP-64 |
| 文件頁數： | 30/152頁 |
| 文件大?。?/td> | 1963K |
| 代理商： | M306V5EESP |
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152
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recom-
mended (see four byte instruction formats in Table 20-12):
1.
Power-up sequence: apply power between V
CC and GND while RESET and SCK are set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse
must be at least t
RST plus two CPU clock cycles. See Table 21-4 on page 165 for minimum pulse width
on RESET pin, t
RST
2.
Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruc-
tion to pin MOSI.
3.
The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable
instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the
0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4.
The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying
the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is applied for a given
address. The Program memory Page is stored by loading the Write Program memory Page instruction
with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 20-11.) Accessing the serial programming interface before the
Flash write operation completes can result in incorrect programming.
5.
A: The EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. An EEPROM memory location is first automatically erased before new
data is written. If polling (RDY/BSY) is not used, the user must wait at least t
WD_EEPROM before issuing the
next byte. (See Table 20-11.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time
by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruc-
tion. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with
the 6 MSB of the address. When using EEPROM page access only byte locations loaded with the Load
EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling
(RDY/BSY) is not used, the used must wait at least t
WD_EEPROM before issuing the next page (See Table
20-9). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6.
Any memory location can be verified by using the Read instruction which returns the content at the
selected address at serial output MISO.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
Power-off sequence (if needed):
Set RESET to “1”.
Turn V
CC power off.
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