參數(shù)資料
型號： M306V5EESP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 14/152頁
文件大小： 1963K
代理商： M306V5EESP
138
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Bits 4:3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of
the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching
to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
.
17.13.5
DIDR0 – Digital Input Disable Register 0
Bits 5:2 – ADC3D:ADC0D: ADC[3:0] Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corre-
sponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the
ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power
consumption in the digital input buffer.
Table 17-6.
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
Free Running mode
0
1
Analog Comparator
0
1
0
External Interrupt Request 0
0
1
Timer/Counter0 Compare Match A
1
0
Timer/Counter0 Overflow
1
0
1
Timer/Counter0 Compare Match B
1
0
Pin Change Interrupt Request
Bit
7
654321
0
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
DIDR0
Read/Write
R
R/W
Initial Value
0
000000
0
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