參數(shù)資料
型號(hào)： M306V5EESP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 20/152頁
文件大?。?/td> 1963K
代理商： M306V5EESP
143
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
19.6
Reading Lock, Fuse and Signature Data from Software
It is possible to read fuse and lock bits from firmware. In addition, firmware can also read data from the device sig-
nature imprint table (see page 149).
Note:
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read
as one.
19.6.1
Reading Lock Bits from Firmware
Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have been set in SPMCSR
will return lock bit values in the destination register. The RFLB and SELFPRGEN bits automatically clear upon
completion of reading the lock bits, or if no LPM instruction is executed within three CPU cycles, or if no SPM
instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
1.
Load the Z-pointer with 0x0001.
2.
Set RFLB and SELFPRGEN bits in SPMCSR.
3.
Issue an LPM instruction within three clock cycles.
4.
Read the lock bits from the LPM destination register.
If successful, the contents of the destination register are as follows.
19.6.2
Reading Fuse Bits from Firmware
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses
are different. To read the Fuse Low Byte (FLB), follow the below procedure:
1.
Load the Z-pointer with 0x0000.
2.
Set RFLB and SELFPRGEN bits in SPMCSR.
3.
Issue an LPM instruction within three clock cycles.
4.
Read the FLB from the LPM destination register.
If successful, the contents of the destination register are as follows.
Refer to Table 20-5 on page 149 for a detailed description and mapping of the Fuse Low Byte.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the proce-
dure above. If successful, the contents of the destination register are as follows.
Refer to Table 20-4 on page 148 for detailed description and mapping of the Fuse High Byte.
Bit
7
654321
0
Rd
–
–––––
LB2
LB1
Bit
7
6
543
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
7
6
543
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
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