參數(shù)資料
型號(hào)： M306V5EESP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 29/152頁
文件大?。?/td> 1963K
代理商： M306V5EESP
151
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
20.5
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled
to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See below.
Figure 20-1. Serial Programming and Verify
Notes:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin.
After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase oper-
ations can be executed.
Note:
In Table 20-10 above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the
internal SPI interface.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
20.5.1
Serial Programming Algorithm
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 and Fig-
ure 21-5 for timing details.
Table 20-10. Pin Mapping Serial Programming
Symbol
Pins
I/O
Description
MOSI
PB0
I
Serial Data in
MISO
PB1
O
Serial Data out
SCK
PB2
I
Serial Clock
VCC
GND
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
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