參數(shù)資料
型號: M306V5EESP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù): 130/152頁
文件大?。?/td> 1963K
代理商: M306V5EESP
M306V5ME-XXXSP
M306V5EESP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
31
Rev. 1.0
2.5.5 Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In
this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 2.5.3 shows the status of the ports
in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when
the WAIT instruction was executed.
Table 2.5.2 Port status during stop mode
Pin
State
Port
Retains status before stop mode
2.5.4 Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC
remains above 4.5V.
Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, and fAD stops in stop mode, peripheral functions
such as the A-D converter and watchdog timer do not function. However, timer B operates provided that
the event counter mode is set to an external pulse, and UARTi (i = 0, 2) functions provided an external
clock is selected. Table 2.5.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop
mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is
executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1.” When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
Table 2.5.3 Port status during wait mode
Pin
State
Port
Retains status before wait mode
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