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參數(shù)資料
| 型號： | M306V5EESP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, PLASTIC, SDIP-64 |
| 文件頁數(shù)： | 22/152頁 |
| 文件大?。?/td> | 1963K |
| 代理商： | M306V5EESP |
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145
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
not, an external low V
CC reset protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply voltage is sufficient.
2.
Keep the AVR core in Power-down sleep mode during periods of low V
CC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the
Flash from unintentional writes.
19.8
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 19-1 shows the typical programming time for
Flash accesses from the CPU.
Note:
1. Minimum and maximum programming time is per individual operation.
19.9
Register Description
19.9.1
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program
memory operations.
Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in SPMCSR will return
the selected data (depending on Z-pointer value) from the device signature imprint table into the destination regis-
ter. See “Device Signature Imprint Table” on page 149 for details.
Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the
data will be lost.
Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either
the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “EEPROM Write
Prevents Writing to SPMCSR” on page 142 for details.
Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes
Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if
no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
Table 19-1.
SPM Programming Time(1)
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms
4.5 ms
Bit
7
6
5
4
3
2
1
0
–
RSIG
CTPB
RFLB
PGWRT
PGERS
SPMEN
SPMCSR
Read/Write
R
R/W
Initial Value
0
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