參數(shù)資料
型號: M12L64164A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 41/45頁
文件大?。?/td> 831K
代理商: M12L64164A-6BG
ES MT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
41/45
Self Refresh Entry & Exit Cycle
*
Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RFC
is required after CKE going high to complete self refresh exit.
7. Burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
A13,A1 2
S el f R ef r es h E n t r y
A u t o R ef r es h
: D o n ' t c a r e
*Not e 2
*No t e 1
t
S S
*Not e 3
*Not e 4
t
R F C
m i n
* No t e 6
S e l f R ef r e s h E xi t
Hi - Z
H i - Z
*No t e 5
* No t e 7
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