參數(shù)資料
型號(hào): M12L64164A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁(yè)數(shù): 14/45頁(yè)
文件大?。?/td> 831K
代理商: M12L64164A-6BG
ES MT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
14/45
COMMANDS
Mode register set command
(
CS
,
RAS
,
CAS
,
WE
= Low)
The M12L64164A has a mode register that defines how the device operates. In
this command, A0 through A13 are the data input pins. After power on, the mode
register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK
(t
RSC
) following this command, the M12L64164A cannot accept any other commands.
Activate command
(CS ,RAS = Low,CAS ,
WE
= High)
The M12L64164A has four banks, each with 4,096 rows.
This command activates the bank selected by A12 and A13 (BS) and a row
address selected by A0 through A11.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
(CS ,RAS ,
WE
= Low,CAS = High )
This command begins precharge operation of the bank selected by A12 and A13
(BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When
A10 is Low, only the bank selected by A12 and A13 is precharged.
After this command, the M12L64164A can’t accept the activate command to the
precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
CLK
CLK
CKE
CKE
CS
CS
RAS
RAS
WE
WE
A12, A13
A12, A13
(Bank select)
A10
A10
Add
Add
CAS
CAS
H
H
Row
Row
Fig. 1 Mode register set
command
Fig. 2 Row address stroble and
bank active command
CLK
CKE
A12, A13
(Bank select)
A10
(Precharge select)
Add
H
Fig. 3 Precharge command
CS
RAS
WE
CAS
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