參數(shù)資料
型號: LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁數(shù): 6/36頁
文件大?。?/td> 538K
代理商: LM12L454CIV
Digital Characteristics
The following specifications apply to the LM12L454 and LM12L458 for V
A
a
e
V
D
a
e
3.3V, unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C.
(Notes 6, 7, and 8)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Unit
(Limit)
V
IN(1)
Logical ‘‘1’’ Input Voltage
V
A
a
e
V
D
a
e
3.6V
V
A
a
e
V
D
a
e
3.0V
ALE, Pin 22
2.0
V (min)
V
IN(0)
Logical ‘‘0’’ Input Voltage
0.7
0.6
V (max)
I
IN(1)
Logical ‘‘1’’ Input Current
V
IN
e
3.3V
0.005
1.0
2.0
m
A (max)
I
IN(0)
Logical ‘‘0’’ Input Current
V
IN
e
0V
b
0.005
b
1.0
b
2.0
m
A (max)
C
IN
D0–D15 Input Capacitance
6
pF
V
OUT(1)
Logical ‘‘1’’ Output Voltage
V
A
a
e
V
D
a
e
3.0V
I
OUT
e b
360
m
A
I
OUT
e b
10
m
A
V
A
a
e
V
D
a
e
3.0V
I
OUT
e
1.6 mA
I
OUT
e
10
m
A
2.4
2.85
V (min)
V (min)
V
OUT(0)
Logical ‘‘0’’ Output Voltage
0.4
0.1
V (max)
I
OUT
TRI-STATE
é
Output Leakage Current
V
OUT
e
0V
V
OUT
e
3.3V
b
0.01
0.01
b
3.0
3.0
m
A (max)
m
A (max)
Digital Timing Characteristics
The following specifications apply to the LM12L454 and LM12L458 for V
A
a
e
V
D
a
e
3.3V, t
r
e
t
f
e
3 ns, and C
L
e
100 pF
on data I/O, INT and DMARQ lines unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all
other limits T
A
e
T
J
e
25
§
C. (Notes 6, 7, and 8)
Symbol
(SeeFigures
8a, 8b, and8c)
Typical
(Note 10)
Limits
(Note 11)
Unit
(Limit)
Parameter
Conditions
1, 3
CS or Address Valid to ALE Low
Set-Up Time
40
ns (min)
2, 4
CS or Address Valid to ALE Low
Hold Time
20
ns (min)
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
30
10
70
ns (min)
ns (max)
17
RD High to TRI-STATE
R
L
e
1 k
X
30
10
110
ns (min)
ns (max)
18
RD Low to Data Valid (Access Time)
30
10
95
ns (min)
ns (max)
6
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