參數(shù)資料
型號(hào): LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁數(shù): 4/36頁
文件大?。?/td> 538K
代理商: LM12L454CIV
Converter Characteristics
The following specifications apply to the LM12L454 and LM12L458 for V
A
a
e
V
D
a
e
3.3V, V
REF
a
e
2.5V, V
REF
b
e
0V,
12-bit
a
sign conversion mode, f
CLK
e
6.0 MHz, R
S
e
25
X
, source impedance for V
REF
a
and V
REF
b
s
25
X
, fully-differential
input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified.
Boldface limits
apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 6, 7, 8, and 9) (Continued)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Unit
(Limit)
8-Bit
a
Sign and ‘‘Watchdog’’ Mode
DC Common Mode Error
g
1/8
LSB
Multiplexer Channel-to-Channel
Matching
g
0.05
LSB
V
IN
a
Non-Inverting Input Range
GND
V
A
a
V (min)
V (max)
V
IN
b
Inverting Input Range
GND
V
A
a
V (min)
V (max)
V
IN
a
b
V
IN
b
Differential Input Voltage Range
b
V
A
a
V
A
a
V (min)
V (max)
V
IN
a
b
V
IN
b
2
Common Mode Input Voltage Range
GND
V
A
a
V (min)
V (max)
PSS
Power Supply
Sensitivity
(Note 15)
Zero Error
V
A
a
e
V
D
a
e
3.3V
g
10%
V
REF
a
e
2.5V, V
REF
b
e
GND
g
0.2
g
0.4
g
0.2
g
1.75
g
2
LSB (max)
LSB (max)
LSB
Full-Scale Error
Linearity Error
C
REF
V
REF
a
/V
REF
b
Input Capacitance
85
pF
C
IN
Selected Multiplexer Channel Input
Capacitance
75
pF
Converter AC Characteristics
The following specifications apply to the LM12L454 and LM12L458 for V
A
a
e
V
D
a
e
3.3V, V
REF
a
e
2.5V, V
REF
b
e
0V,
12-bit
a
sign conversion mode, f
CLK
e
6.0 MHz, R
S
e
25
X
, source impedance for V
REF
a
and V
REF
b
s
25
X
, fully-differential
input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified.
Boldface limits
apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 6, 7, 8, and 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Unit
(Limit)
Clock Duty Cycle
50
%
40
60
% (min)
% (max)
t
C
Conversion Time
13-Bit Resolution,
Sequencer State S5(Figure 11)
44 (t
CLK
)
44 (t
CLK
)
a
50 ns
(max)
9-Bit Resolution,
Sequencer State S5(Figure 11)
21 (t
CLK
)
21 (t
CLK
)
a
50 ns
(max)
t
A
Acquisition Time
Sequencer State S7(Figure 11)
Built-in minimum for 13-Bits
9 (t
CLK
)
9 (t
CLK
)
a
50 ns
(max)
Built-in minimum for 9-Bits and
‘‘Watchdog’’ mode
2 (t
CLK
)
2 (t
CLK
)
a
50 ns
(max)
t
Z
Auto-Zero Time
Sequencer State S2(Figure 11)
76 (t
CLK
)
76 (t
CLK
)
a
50 ns
(max)
t
CAL
Full Calibration Time
Sequencer State S2(Figure 11)
4944 (t
CLK
)
4944 (t
CLK
)
a
50 ns
(max)
Throughput Rate
(Note 18)
107
106
kHz
(min)
t
WD
‘‘Watchdog’’ Mode Comparison Time
Sequencer States S6, S4,
and S5(Figure 11)
11 (t
CLK
)
11 (t
CLK
)
a
50 ns
(max)
t
PU
Power-Up Time
10
ms
t
WU
Wake-Up Time
10
ms
4
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參數(shù)描述
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LM12L458CIVF 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL I/O DAS - Bulk