參數(shù)資料
型號： LM12L454CIV
英文描述： IC-SM-12 BIT DAS
中文描述： 集成電路的Sm - DAS的12位
文件頁數(shù)： 16/36頁
文件大小： 538K
代理商： LM12L454CIV
Pin Description
V
A
a
These are the analog and digital supply voltage
V
D
a
pins. The LM12L454/8’s supply voltage operating
range is
a
3.0V to
a
5.5V. Accuracy is guaranteed
only if V
A
a
and V
D
a
are connected to the same
power supply. Each pin should have a parallel
combination of 10
m
F (electrolytic or tantalum) and
0.1
m
F (ceramic) bypass capacitors connected be-
tween it and ground.
D0–D15 The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are de-
signed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. These pins allows the user a
means of instruction input and data output. With a
logic
high
applied to the
BW
pin, data lines D8–
D15 are placed in a high impedance state and data
lines D0–D7 are used for instruction input and
data output when the LM12L454/8 is connected to
an 8-bit wide data bus. A logic
low
on the
BW
pin
allows the LM12L454/8 to exchange information
over a 16-bit wide data bus.
RD
This is the input for the active low READ bus con-
trol signal. The data input/output TRI-STATE buff-
ers, as selected by the logic signal applied to the
BW
pin, are enabled when RD and CS are both
low. This allows the LM12L454/8 to transmit infor-
mation onto the databus.
WR
This is the input for the active low WRITE bus con-
trol signal. The data input/output TRI-STATE buff-
ers, as selected by the logic signal applied to the
BW
pin, are enabled when WR and CS are both
low. This allows the LM12L454/8 to receive infor-
mation from the databus.
CS
This is the input for the active low Chip Select con-
trol signal. A logic low should be applied to this pin
only during a READ or WRITE access to the
LM12L454/8. The internal clocking is halted and
conversion stops while Chip Select is low. Conver-
sion resumes when the Chip Select input signal
returns high.
ALE
This is the Address Latch Enable input. It is used in
systems containing a multiplexed databus. When
ALE is asserted
high
, the LM12L454/8 accepts
information on the databus as a valid address. A
high-to-low transition will latch the address data on
A0–A4 and the logic state on the CS input. Any
changes on A0–A4 and CS while ALE is low will
not affect the LM12L454/8. See Figure 8a. When
a non-multiplexed bus is used, ALE is continuously
asserted
high
. See Figure 8b.
CLK
This
LM12L454/8 operates with an input clock frequen-
cy in the range of 0.05 MHz to 8 MHz.
is
the
external
clock
input
pin.
The
A0–A4
These are the LM12L454/8’s address lines. They
are used to access all internal registers, Conver-
sion FIFO, and Instruction
RAM
.
SYNC
This is the synchronization input/output. When
used as an output, it is designed to drive capacitive
loads of 100 pF or less. External buffers are nec-
essary for driving higher load capacitances. SYNC
is an
input
if the Configuration register’s ‘‘I/O Se-
lect’’ bit is
low
. A rising edge on this pin causes
the internal S/H to hold the input signal. The
next rising clock edge either starts a conver-
sion or makes a comparison to a programma-
ble limit depending on which function is re-
quested by a programming instruction. This pin
will be an
output
if ‘‘I/O Select’’ is set
high
.
The SYNC output goes high when a conver-
sion or a comparison is started and low when
completed. (See Section 2.2). An internal reset
after power is first applied to the LM12L454/8
automatically sets this pin as an input.
BW
This is the Bus Width input pin. This input al-
lows the LM12L454/8 to interface directly with
either an 8- or 16-bit databus. A logic high sets
the width to 8 bits and places D8–D15 in a
high impedance state. A logic low sets the
width to 16 bits.
INT
This is the active low interrupt output. This out-
put is designed to drive capacitive loads of
100 pF or less. External buffers are necessary
for driving higher load capacitances. An inter-
rupt signal is generated any time a non-
masked interrupt condition takes place. There
are eight different conditions that can cause
an interrupt. Any interrupt is reset by reading
the Interrupt Status register. (See Section 2.3.)
DMARQ
This is the active high Direct Memory Access
Request output. This output is designed to
drive capacitive loads of 100 pF or less. Exter-
nal buffers are necessary for driving higher
load capacitances. It goes high whenever the
number of conversion results in the conversion
FIFO equals a programmable value stored in
the Interrupt Enable register. It returns to a log-
ic low when the FIFO is empty.
GND
This is the LM12L454/8 ground connection. It
should be connected to a low resistance and
inductance analog ground return that connects
directly to the system power supply ground.
IN0–IN7
(IN0–IN3
LM12L454
These are the eight (LM12L458) or four
(LM12L454) analog inputs. A given channel is
selected through the instruction RAM. Any of
the channels can be configured as an indepen-
dent single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate
as a fully differential pair.
S/H IN
a
S/H IN
b
MUXOUT
a
These are the LM12L454’s non-inverting and
MUXOUT
b
inverting outputs from the internal multiplexer.
V
REF
b
This is the negative reference input. The
LM12L454/8 operate with 0V
s
V
REF
b
s
V
REF
a
. This pin should be bypassed to
ground with a parallel combination of 10
m
F
and 0.1
m
F (ceramic) capacitors.
V
REF
a
This is the positive reference input. The
LM12L454/8 operate with 0V
s
V
REF
a
s
V
A
a
. This pin should be bypassed to ground
with a parallel combination of 10
m
F and
0.1
m
F (ceramic) capacitors.
N.C.
This is a no connect pin.
These are the LM12L454’s non-inverting and
inverting inputs to the internal S/H.
16
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