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| 型號(hào)： | LM12L454CIV |
| 英文描述： | IC-SM-12 BIT DAS |
| 中文描述： | 集成電路的Sm - DAS的12位 |
| 文件頁(yè)數(shù)： | 23/36頁(yè) |
| 文件大小： | 538K |
| 代理商： | LM12L454CIV |
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2.0 Internal User-Programmable Registers
(Continued)
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 0001 to 1111, representing 1 to 31 con-
versions stored in the FIFO. A user-programmed value of
0000 has no meaning. See Section 3.0 for more FIFO infor-
mation.
The completion of the short, single-sampled auto-zero cali-
bration generates
Interrupt 3
.
The completion of a full auto-zero and linearity self-calibra-
tion generates
Interrupt 4
.
Interrupt 5
is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM
‘‘00’’) set to ‘‘1’’.
Interrupt 7
is issued after a short delay (10 ms typ) while
the LM12L454/8 returns from Standby mode to active oper-
ation using the Configuration register’s Bit 4. This short de-
lay allows the internal analog circuitry to settle sufficiently,
ensuring accurate conversion results.
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4–A1, BW
e
0) or 1001x (A4–A0, BW
e
1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by plac-
ing a ‘‘1’’ in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to ‘‘1’’ in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the
eight internal interrupts.
Bit 0
enables an external interrupt when an internal ‘‘watch-
dog’’ comparison limit interrupt has taken place.
Bit 1
enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt
Enable register.
Bit 2
enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
Bit 3
enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4
enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
Bit 5
enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6
is a ‘‘Don’t Care’’.
Bit 7
enables an external interrupt when the LM12L454/8
return from power-down to active mode.
Bits 8–10
form the storage location of the user-programma-
ble value against which the Sequencer’s address is com-
pared. When the Sequencer reaches an address that is
equal to the value stored in Bits 8–10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to ‘‘1’’,
an external interrupt will appear at pin 31 (INT).
The value stored in bits 8–10 ranges from 000 to 111, rep-
resenting 0 to 7 instructions stored in the Instruction RAM.
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’, the Sequencer is started by placing
a ‘‘1’’ in the Configuration register’s START bit. Setting the
INT 1 trigger value to 000
does not generate
an INT 1 the
first
time the Sequencer retrieves and decodes Instruction
000. The Sequencer
generates
INT 1 (by placing a ‘‘1’’ in
the Interrupt Status register’s Bit 1) the
second time and
after
the Sequencer encounters Instruction 000. It is impor-
tant to remember that the Sequencer continues to operate
even if an Instruction interrupt (INT 1) is internally or exter-
nally generated. The only mechanisms that stop the Se-
quencer are an instruction with the PAUSE bit set to ‘‘1’’
(halts before instruction execution), placing a ‘‘0’’ in the
Configuration register’s START bit, or placing a ‘‘1’’ in the
Configuration register’s RESET bit.
Bits 11–15
hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable reg-
ister is set to ‘‘1’’, an external interrupt will appear at pin 31
(INT).
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW
e
0) or 1010x (A4–A0, BW
e
1). The corresponding
flag in the Interrupt Status register goes high (‘‘1’’) any time
that an interrupt condition takes place, whether an interrupt
is enabled or disabled in the Interrupt Enable register. Any
of the active (‘‘1’’) Interrupt Status register flags are reset to
‘‘0’’ whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0
is set to ‘‘1’’ when a ‘‘watchdog’’ comparison limit
interrupt has taken place.
Bit 1
is set to ‘‘1’’ when the Sequencer has reached the
address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2
is set to ‘‘1’’ when the Conversion FIFO’s limit, stored
in Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3
is set to ‘‘1’’ when the single-sampled auto-zero has
been completed.
Bit 4
is set to ‘‘1’’ when an auto-zero and full linearity self-
calibration has been completed.
Bit 5
is set to ‘‘1’’ when a Pause interrupt has been generat-
ed.
Bit 6
is a ‘‘Don’t Care’’.
Bit 7
is set to ‘‘1’’ when the LM12L454/8 return from power-
down to active mode.
Bits 8–10
hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15
hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
2.6 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1,
BW
e
0) or 1101x (A4–A0, BW
e
1). This register is used
in tandem with the Limit
Y
1 and Limit
Y
2 registers in the
Instruction RAM. Whenever a given instruction’s input volt-
age exceeds the limit set in its corresponding Limit register
(
Y
1 or
Y
2), a bit, corresponding to the instruction number,
is set in the Limit Status register. Any of the active (‘‘1’’)
Limit Status flags are reset to ‘‘0’’ whenever this register is
23
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| LM12L458 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
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| LM12L458CIV | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIV/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIVF | 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL I/O DAS - Bulk |
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