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| 型號(hào)： | LM12L454CIV |
| 英文描述： | IC-SM-12 BIT DAS |
| 中文描述： | 集成電路的Sm - DAS的12位 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 538K |
| 代理商： | LM12L454CIV |
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2.0 Internal User-Programmable Registers
(Continued)
read or a device reset is issued (see Bit 1 in the Configura-
tion register). This register holds the status of limits
Y
1 and
Y
2 for each of the eight instructions.
Bits 0–7
show the Limit
Y
1 status. Each bit will be set high
(‘‘1’’) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit
Y
1 reg-
ister. When, for example, instruction 3 is a ‘‘watchdog’’ op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruc-
tion 3’s Limit
Y
1 register, Bit 3 in the Limit Status register
will be set to a ‘‘1’’.
Bits 8–15
show the Limit
Y
2 status. Each bit will be set
high (‘‘1’’) when the corresponding instruction’s input volt-
age exceeds the threshold stored in the instruction’s Limit
Y
2 register. When, for example, the input to instruction 6
meets the value stored in instruction 6’s Limit
Y
2 register,
Bit 14 in the Limit Status register will be set to a ‘‘1’’.
2.7 TIMER
The LM12L454/8 have an on-board 16-bit timer that in-
cludes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0
through 2
21
clock cycles in steps of 2
5
. This time interval
can be used to delay the execution of instructions. It can
also be used to slow the conversion rate when converting
slowly changing signals. This can reduce the amount of re-
dundant data stored in the FIFO and retrieved by the con-
troller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW
e
0) or 1011x (A4–A0, BW
e
1) and is pre-
loaded automatically. Bits 0–7 hold the preset value’s low
byte and Bits 8–15 hold the high byte. The Timer is activat-
ed by the Sequencer only if the current instruction’s Bit 9 is
set
(‘‘1’’).
If
the
equivalent
(0
s
N
s
2
16
b
1) is written inside the 16-bit Timer register
and the Timer is enabled by setting an instruction’s bit 9 to a
‘‘1’’, the Sequencer will delay the same instruction’s execu-
tion by halting at state 3 (S3), as shown in Figure 11, for
32
c
N
a
2 clock cycles.
decimal
value
‘‘N’’
2.8 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO inter-
rupt be enabled. The voltage on the DMARQ pin goes high
when the number of conversions in the FIFO equals the
5-bit value stored in the Interrupt Enable register (bits 11–
15). The voltage on the INT pin goes low at the same time
as the voltage on the DMARQ pin goes high. The voltage on
the DMARQ pin goes low when the FIFO is emptied. The
Interrupt Status register must be read to clear the FIFO in-
terrupt flag in order to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
databus connection (a logic ‘‘0’’ applied to the BW pin). Us-
ing this bus width allows DMA controllers that have single
address Read/Write capability to easily unload the FIFO.
Using DMA on an 8-bit databus is more difficult. Two read
operations (low byte, high byte) are needed to retrieve each
conversion result from the FIFO. Therefore, the DMA con-
troller must be able to repeatedly access two constant ad-
dresses when transferring data from the LM12L454/8 to the
host system.
3.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100 (A4–
A1, BW
e
0) or 1100x (A4–A0, BW
e
1). This register has
32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits
a
sign mode or
‘‘1110’’ in the 8 bits
a
sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold
either the sign bit, extending the register’s two’s comple-
ment data format to a full sixteen bits or the instruction ad-
dress that generated the conversion and the resulting data.
These modes are selected according to the logic state of
the Configuration register’s Bit 5.
The FIFO status should be read in the Interrupt Status regis-
ter (Bits 11–15) to determine the number of conversion re-
sults that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12L454/8’s interrupt capability be used to inform the
system controller that the FIFO is full.
The lower portion (A0
e
0) of the data word (Bits 0–7)
should be read first followed by a read of the upper portion
(A0
e
1) when using the 8-bit bus width (BW
e
1). Reading
the upper portion first causes the data to shift down, which
results in loss of the lower byte.
Bits 0–12
hold 12-bit
a
sign conversion data.
Bits 0–3
will
be 1110 (LSB) when using 8-bit plus sign resolution.
Bits 13–15
hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable registers’s Bits 11–15 to 1111
and the Interrupt Enable register’s Bit 2 to a ‘‘1’’. This gen-
erates an external interrupt when the 31st conversion is
stored in the FIFO. This gives the host processor a chance
to send a ‘‘0’’ to the LM12L454/8’s Start bit (Configuration
register) and halt the ADC before it completes the 32nd
conversion. The Sequencer halts after the current (32) con-
version is completed. The conversion data is then trans-
ferred to the FIFO and occupies the 32nd location. FIFO
overflow is avoided if the Sequencer is halted before the
start of the 32nd conversion by placing a ‘‘0’’ in the Start bit
(Configuration register). It is important to remember that the
Sequencer
continues to operate even if a FIFO interrupt
(INT 2) is internally or externally generated
. The only
mechanisms that stop the Sequencer are an instruction with
the PAUSE bit set to ‘‘1’’ (halts before instruction execu-
tion), placing a ‘‘0’’ in the Configuration register’s START
bit, or placing a ‘‘1’’ in the Configuration register’s RESET
bit.
24
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| LM12L458 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
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| LM12L458CIV | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIV/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIVF | 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL I/O DAS - Bulk |
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