參數(shù)資料
型號(hào): LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁(yè)數(shù): 15/36頁(yè)
文件大?。?/td> 538K
代理商: LM12L454CIV
Timing Diagrams
V
A
a
e
V
D
a
e a
3.3V, t
R
e
t
F
e
3 ns, C
L
e
100 pF for the INT, DMARQ, D0–D15 outputs. (Continued)
TL/H/11711–20
FIGURE 8b. Non-Multiplexed Data Bus (ALE
e
1)
8: RD pulse width
9: RD high to next RD or WR low
11: WR pulse width
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
V
A
a
e
V
D
a
e a
3.3V, t
R
e
t
F
e
3 ns, C
L
e
100 pF for the INT, DMARQ, D0–D15 outputs.
TL/H/11711–21
FIGURE 8c. Interrupt and DMARQ
22: INT high from RD low
23: DMARQ low from RD low
15
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