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| 型號： | LM12L454CIV |
| 英文描述： | IC-SM-12 BIT DAS |
| 中文描述： | 集成電路的Sm - DAS的12位 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 538K |
| 代理商： | LM12L454CIV |
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2.0 Internal User-Programmable Registers
2.1 INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit ‘‘RAM pointer’’ in the Configuration register.
The eight instructions are located at addresses 0000
through 0111 (A4–A1, BW
e
0) when using a 16-bit wide
data bus or at addresses 00000 through 01111 (A4–A0,
BW
e
1) when using an 8-bit wide data bus. They can be
accessed and programmed in random order.
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation:
The Sequencer should be stopped by setting the RESET
bit to a ‘‘1’’ or by resetting the START bit in the Configu-
ration Register and waiting for the current instruction to
finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a ‘‘1’’ to the
Configuration Register’s RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit ‘‘RAM Pointer’’, bits D8
and D9. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to ‘‘00’’. This section provides
multiplexer channel selection, as well as resolution, acquisi-
tion time, etc. The second 16-bit section holds ‘‘watchdog’’
limit
Y
1, its sign, and an indicator that shows that an inter-
rupt can be generated if the input signal is greater or less
than the programmed limit. The third 16-bit section holds
‘‘watchdog’’ limit
Y
2, its sign, and an indicator that shows
that an interrupt can be generated if the input signal is great-
er or less than the programmed limit.
Instruction RAM ‘‘00’’
Bit 0
is the LOOP bit. It indicates the last instruction to be
executed in any instruction sequence when it is set to a ‘‘1’’.
The next instruction to be executed will be instruction 0.
Bit 1
is the PAUSE bit. This controls the Sequencer’s opera-
tion. When the PAUSE bit is set (‘‘1’’), the Sequencer will
stop after reading the current instruction, but before execut-
ing it and the start bit, in the Configuration register, is auto-
matically reset to a ‘‘0’’. Setting the PAUSE also causes an
interrupt to be issued. The Sequencer is restarted by placing
a ‘‘1’’ in the Configuration register’s Bit 0 (Start bit).
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’, the Sequencer retrieves Instruction
000, decodes it, and waits for a ‘‘1’’ to be placed in the
Configuration’s START bit. The START bit value of ‘‘0’’
‘‘overrides’’ the action of Instruction 000’s PAUSE bit when
the Sequencer is started. Once started, the Sequencer exe-
cutes Instruction 000 and retrieves, decodes, and executes
each of the remaining instructions. No PAUSE Interrupt (INT
5) is generated the first time the Sequencer executes In-
struction 000 having a PAUSE bit set to ‘‘1’’. When the Se-
quencer encounters a LOOP bit or completes all eight in-
structions, Instruction 000 is retrieved and decoded. A set
PAUSE bit in Instruction 000 now halts the Sequencer be-
fore the instruction is executed.
Bits 2–4
select which of the eight input channels (‘‘000’’ to
‘‘111’’ for IN0–IN7) will be configured as non-inverting in-
puts to the LM12L458’s ADC. (See Page 22, Table I.) They
select which of the four input channels (‘‘000’’ to ‘‘011’’ for
IN0–IN4) will be configured as non-inverting inputs to the
LM12L454’s ADC. (See Page 22, Table II.)
Bits 5–7
select which of the seven input channels (‘‘001’’ to
‘‘111’’ for IN1 to IN7) will be configured as inverting inputs to
the LM12L458’s ADC. (See Page 22, Table I.) They select
which of the three input channels (‘‘001’’ to ‘‘011’’ for IN1–
IN4)
will
be
configured
as
LM12L454’s ADC. (See Page 22, Table II.) Fully differential
operation is created by selecting two multiplexer channels,
one operating in the non-inverting mode and the other oper-
ating in the inverting mode. A code of ‘‘000’’ selects ground
as the inverting input for single ended operation.
inverting
inputs
to
the
Bit 8
is the SYNC bit. Setting Bit 8 to ‘‘1’’ causes the Se-
quencer to suspend operation at the end of the internal
S/H’s acquisition cycle and to wait until a rising edge ap-
pears at the SYNC pin. When a rising edge appears, the
S/H acquires the input signal magnitude and the ADC per-
forms a conversion on the clock’s next rising edge. When
the SYNC pin is used as an input, the Configuration regis-
ter’s ‘‘I/O Select’’ bit (Bit 7) must be set to a ‘‘0’’. With
SYNC configured as an input, it is possible to synchronize
the start of a conversion to an external event. This is useful
in applications such as digital signal processing (DSP)
where the exact timing of conversions is important.
When the LM12L454/8 are used in the ‘‘watchdog’’ mode
with external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit
Y
1 (found in Instruction RAM ‘‘01’’) and the
second rising edge initiates the comparison of the same
analog input signal with Limit
Y
2 (found in Instruction RAM
‘‘10’’).
Bit 9
is the TIMER bit. When Bit 9 is set to ‘‘1’’, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no ‘‘watchdog’’ compari-
sons or analog-to-digital conversions will be performed.
Bit 10
selects the ADC conversion resolution. Setting Bit 10
to ‘‘1’’ selects 8-bit
a
sign and when reset to ‘‘0’’ selects
12-bit
a
sign.
Bit 11
is the ‘‘watchdog’’ comparison mode enable bit.
When operating in the ‘‘watchdog’’ comparison mode, the
selected analog input signal is compared with the program-
mable values stored in Limit
Y
1 and Limit
Y
2 (see Instruc-
tion RAM ‘‘01’’ and Instruction RAM ‘‘10’’). Setting Bit 11 to
‘‘1’’ causes two comparisons of the selected analog input
signal with the two stored limits. When Bit 11 is reset to ‘‘0’’,
an 8-bit
a
sign or 12-bit
a
sign (depending on the state of
Bit 10 of Instruction RAM ‘‘00’’) conversion of the input sig-
nal can take place.
18
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LM12L458 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
| LM12L458_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
| LM12L458CIV | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIV/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| LM12L458CIVF | 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL I/O DAS - Bulk |
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