參數(shù)資料
型號: LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁數(shù): 20/36頁
文件大?。?/td> 538K
代理商: LM12L454CIV
2.0 Internal User-Programmable Registers
(Continued)
A4
A3
A2
A1
A0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
0
0
to
1
0
(RAM Pointer
e
00)
Instruction RAM
R/W
(MUXOUT
b
)
*
V
IN
b
(MUXOUT
a
)
*
V
IN
a
0
0
Pause
Loop
1
1
0
0
to
1
0
R/W
Watch-
dog
0
1
Acquisition Time
8/12
Timer
Sync
1
1
0
0
to
1
0
(RAM Pointer
e
01)
Instruction RAM
R/W
0
0
Comparison Limit
Y
1
1
1
0
0
to
1
0
R/W
0
1
Don’t Care
l
/
k
Sign
1
1
0
0
to
1
0
(RAM Pointer
e
10)
Instruction RAM
R/W
0
0
Comparison Limit
Y
2
1
1
0
0
to
1
0
R/W
0
1
Don’t Care
l
/
k
Sign
1
1
1
0
0
0
0
Configuration
Register
R/W
I/O
Sel
Auto
Zero
ec
Chan
Mask
Stand-
by
Full
Cal
Auto-
Zero
Reset
Start
1
0
0
0
1
R/W
Don’t Care
DIAG
2
Test
e
0
RAM Pointer
1
0
0
1
0
Interrupt Enable
Register
R/W
INT7
Don’t
Care
INT5
INT4
INT3
INT2
INT1
INT0
1
0
0
1
1
R/W
Number of Conversions in Conversion
FIFO to Generate INT2
Sequencer Address to
Generate INT1
1
0
1
0
0
Interrupt Status
Register
R
INST7
‘‘0’’
INST5
INST4
INST3
INST2
INST1
INST0
1
0
1
0
1
R
Actual Number of Conversions Results
in Conversion FIFO
Address of Sequencer
Instruction
being Executed
1
0
1
1
0
Register
Timer
R/W
Timer Preset: Low Byte
1
0
1
1
1
R/W
Timer Preset: High Byte
1
1
0
0
0
Conversion
FIFO
R
Conversion Data: LSBs
1
1
0
0
1
R
Address or Sign
Sign
Conversion Data: MSBs
1
1
0
1
0
Limit Status
Register
R
Limit
Y
1 Status
1
1
0
1
1
R
Limit
Y
2 Status
*
LM12L454 (Refer to Table II).
2
LM12L458 only. Must be set to ‘‘0’’ for the LM12L454.
FIGURE 10. LM12L454/8 Memory Map for 8-Bit Wide Databus (BW
e
‘‘1’’ and Test Bit
e
‘‘0’’)
20
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