參數(shù)資料
型號: LAN9117-MD
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 73/131頁
文件大?。?/td> 1531K
代理商: LAN9117-MD
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
73
Revision 1.1 (05-17-05)
DATASHEET
5.3.1
ID_REV—Chip ID and Revision
This register contains the ID and Revision fields for this design.
5.3.2
IRQ_CFG—Interrupt Configuration Register
This register configures and indicates the state of the IRQ signal.
ACh
AFC_CFG
Automatic Flow Control Configuration
00000000h
B0h
E2P_CMD
EEPROM command (The EEPROM is
indexed through this register)
00000000h
B4h
E2P_DATA
EEPROM Data
00000000h
B8h - FCh
RESERVED
Reserved for future use
-
Offset:
50h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-16
Chip ID.
This read-only field identifies this design
RO
0117h
15-0
Chip Revision.
This is the current revision of the chip.
RO
0001h
Offset:
54h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:24
Interrupt Deassertion Interval (INT_DEAS).
This field determines the
Interrupt Deassertion Interval for the Interrupt Request in multiples of 10
microseconds.
Writing zeros to this field disables the INT_DEAS Interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-
zero value is written to the INT_DEAS field, any subsequent interrupts
will obey the new setting.
Note:
The Interrupt Deassertion interval does not apply to the PME
interrupt.
R/W
0
23-15
Reserved
RO
-
Table 5.1 LAN9117 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
SYMBOL
REGISTER NAME
DEFAULT
相關PDF資料
PDF描述
LAN9117-MT HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9118 HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
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