參數(shù)資料
型號： LAN9117-MD
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 116/131頁
文件大小： 1531K
代理商： LAN9117-MD
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
116
SMSC LAN9117
DATASHEET
6.1.2
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9117, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
Table 6.2, "Read After Read Timing Rules"
. The host
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
Table 6.2
also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
RX_CFG
45
1
TX_CFG
45
1
HW_CFG
45
1
RX_DP_CTRL
45
1
RX_FIFO_INF
0
0
TX_FIFO_INF
135
3
PMT_CTRL
315
7
GPIO_CFG
45
1
GPT_CFG
45
1
GPT_CNT
135
3
ENDIAN
45
1
FREE_RUN
180
4
RX_DROP
0
0
MAC_CSR_CMD
45
1
MAC_CSR_DATA
45
1
AFC_CFG
45
1
E2P_CMD
45
1
E2P_DATA
45
1
Table 6.1 Read After Write Timing Rules (continued)
REGISTER NAME
MINIMUM WAIT TIME FOR READ
FOLLOWING ANY WRITE CYCLE
(IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING T
CYCLE
OF 45NS)
相關(guān)PDF資料
PDF描述
LAN9117-MT HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9118 HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MD HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MT HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN91C100-FD-SS FEAST Fast Ethernet Controller with Full Duplex Capability
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAN9117-MT 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9118 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_05 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_07 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118-MD 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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