參數(shù)資料
型號： LAN9118-MT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： ROHS COMPLIANT, TQFP-100
文件頁數(shù)： 1/6頁
文件大?。?/td> 213K
代理商： LAN9118-MT
SMSC LAN9118
PRODUCT PREVIEW
Revision 0.5 (09-09-04)
Data Brief
PRODUCT FEATURES
LAN9118
High-Performance
Single-Chip 10/100
Non-PCI Ethernet
Controller
Highlights
■
Optimized for high-data rate applications such as
video, high-definition video and multi-media
applications
■
Efficient architecture with low CPU overhead; easily
interfaces to most Embedded CPU’s
■
Reduces system and design costs
Target Applications
■
Cable, satellite, and IP set-top boxes
■
Digital video recorders
■
High definition televisions
■
Digital music jukeboxes
■
Digital media clients/servers
■
DVD recorders/players
■
Home gateways
■
Video-over IP Solutions
■
Wireless routers & access points
■
IP PBX & video phones
Key Benefits
■
Supports high and ultra-high performance
applications
—
Highest performing non-PCI Ethernet controller in the
market
—
32-bit interface with 45ns bus cycle times
—
Burst-mode read support
■
Eliminates dropped packets
—
Internal SRAM can store over 200 packets
—
Supports automatic or host-triggered PAUSE and back-
pressure flow control
■
Minimizes CPU overhead
—
Supports Slave-DMA
—
Interrupt Pin with Programmable Hold-off timer
■
Reduces system cost and increases design flexibility
—
SRAM-like interface easily interfaces to most
Embedded CPU’s or SoC’s
—
Low-cost, low-pin count non-PCI interface for
embedded designs
■
Architected for Low Power
—
Numerous power management modes
—
Wake on LAN
—
Magic packet wakeup
—
Wakeup indicator event signal
—
Link Status Change
■
Single chip Ethernet controller
—
Fully compliant with IEEE 802.3/802.3u standards
—
Integrated Ethernet MAC and PHY
—
10BASE-T and 100BASE-TX support
—
Full- and Half-duplex support
—
Full-duplex flow control
—
Backpressure for half-duplex flow control
—
Preamble generation and removal
—
Automatic 32-bit CRC generation and checking
—
Automatic payload padding and pad removal
—
Loop-back modes
■
Flexible address filtering modes
—
One 48-bit perfect address
—
64 hash-filtered multicast addresses
—
Pass all multicast
—
Promiscuous mode
—
Inverse filtering
—
Pass all incoming with status report
—
Disable reception of broadcast packets
■
Integrated Ethernet PHY
—
Auto-negotiation
—
Automatic polarity detection and correction
■
High-Performance host bus interface
—
Simple, SRAM-like interface
—
32/16-bit data bus
—
Large, 16Kbyte FIFO memory that can be allocated to
RX or TX functions
—
One configurable Host interrupt
■
Miscellaneous features
—
Low profile 100-pin TQFP package
—
Integral 1.8V regulator
—
General Purpose Timer
—
Support for optional EEPROM
—
Support for 3 status LEDs multiplexed with
Programmable GPIO signals
■
3.3V Power Supply with 5V tolerant I/O
■
0 to 70
°
C
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