參數(shù)資料
型號: LAN9117-MD
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 120/131頁
文件大?。?/td> 1531K
代理商: LAN9117-MD
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
120
SMSC LAN9117
DATASHEET
Note:
An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
6.5
RX Data FIFO Direct PIO Burst Reads
In this mode the upper address inputs are not decoded, and any burst read of the LAN9117 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9117. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or
WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)
or Read Enable (nRD). When either or both of these control signals go high, they must remain high
for the period specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Table 6.5 RX Data FIFO Direct PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
cycle
Read Cycle Time
45
ns
t
csl
nCS, nRD Assertion Time
32
ns
t
csh
nCS, nRD Deassertion Time
13
ns
t
csdv
nCS, nRD Valid to Data Valid
30
ns
t
asu
Address, FIFO_SEL Setup to nCS, nRD Valid
0
ns
t
ah
Address, FIFO_SEL Hold Time
0
ns
t
don
Data Buffer Turn On Time
0
ns
t
doff
Data Buffer Turn Off Time
7
ns
t
doh
Data Output Hold Time
0
ns
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