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| 型號(hào)： | LAN9117-MD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 46/131頁(yè) |
| 文件大小： | 1531K |
| 代理商： | LAN9117-MD |
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
46
SMSC LAN9117
DATASHEET
3.13
TX Data Path Operation
Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may
be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command
‘A’ and TX command ‘B’). The TX command instructs the LAN9117 on the handling of the associated
buffer. Packet boundaries are delineated using control bits within the TX command.
The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended
to the corresponding TX status DWORD. All Packet Tag fields must have the same value for all buffers
in a given packet. If tags differ between buffers in the same packet the TXE error will be asserted. Any
value may be chosen for a Packet Tag as long as all tags in the same Packet are identical. Packet
Tags also provide a method of synchronization between transmitted packets and their associated
status. Software can use unique Packet Tags to assist with validating matching status completions.
Note 3.13
The use of packet tags is not required by the hardware. This is a software LAN driver only
application example for use of this field.
A Packet Length field in the TX command specifies the number of bytes in the associated packet. All
Packet Length fields must have the same value for all buffers in a given packet. Hardware compares
the Packet Length field and the actual amount of data received by the Ethernet controller. If the actual
packet length count does not match the Packet Length field as defined in the TX command, the
Transmitter Error (TXE) flag is asserted.
The LAN9117 can be programmed to start payload transmission of a buffer on a byte boundary by
setting the “Data Start Offset” field in the TX command. The “Data Start Offset” field points to the actual
start of the payload data within the first 8 DWORDs of the buffer. Data before the “Data Start Offset”
pointer will be ignored. When a packet is split into multiple buffers, each successive buffer may begin
on any arbitrary byte.
The LAN9117 can be programmed to strip padding from the end of a transmit packet in the event that
the end of the packet does not align with the host burst boundary. This feature is necessary when the
LAN9117 is operating in a system that always performs multi-word bursts. In such cases the LAN9117
must guarantee that it can accept data in multiples of the Burst length regardless of the actual packet
length. When configured to do so, the LAN9117 will accept extra data at the end of the packet and will
remove the extra padding before transmitting the packet. The LAN9117 automatically removes data up
to the boundary specified in the Buffer End Alignment field specified in each TX command.
The host can instruct the LAN9117 to issue an interrupt when the buffer has been fully loaded into the
TX FIFO contained in the LAN9117 and transmitted. This feature is enabled through the TX command
‘Interrupt on Completion’ field.
Upon completion of transmission, irrespective of success or failure, the status of the transmission is
written to the TX status FIFO. TX status is available to the host and may be read using PIO operations.
An interrupt can be optionally enabled by the host to indicate the availability of a programmable
number TX status DWORDS.
Before writing the TX command and payload data to the TX FIFO, the host must check the available
TX FIFO space by performing a PIO read of the TX_FIFO_INF register. The host must ensure that it
does not overfill the TX FIFO or the TX Error (TXE) flag will be asserted.
The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’.
After writing the command, the host can then move the payload data into the TX FIFO. TX status
DWORD’s are stored in the TX status FIFO to be read by the host at a later time upon completion of
the data transmission onto the wire.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LAN9117-MT | HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER |
| LAN9118 | HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER |
| LAN9118-MD | HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER |
| LAN9118-MT | HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER |
| LAN91C100-FD-SS | FEAST Fast Ethernet Controller with Full Duplex Capability |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN9117-MT | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN9118 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
| LAN9118_05 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
| LAN9118_07 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
| LAN9118-MD | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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