參數(shù)資料
型號： LAN9117-MD
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 52/131頁
文件大?。?/td> 1531K
代理商： LAN9117-MD
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
52
SMSC LAN9117
DATASHEET
3.13.5
Calculating Actual TX Data FIFO Usage
The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:
■
TX command 'A' is stored in the TX data FIFO for every TX buffer
■
TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX
command 'A'
■
Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before
the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX
data FIFO.
■
Payload from each buffer within a Packet is written into the TX data FIFO.
■
Any DWORD-long data added as part of the End Padding is removed from each buffer before the
data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the
TX data FIFO
3.13.6
Transmit Examples
3.13.6.1
TX Example 1
In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three
buffers. The three buffers are as follows:
Buffer 0:
■
7-Byte “Data Start Offset”
■
79-Bytes of payload data
■
16-Byte “Buffer End Alignment”
Buffer 1:
■
0-Byte “Data Start Offset”
■
15-Bytes of payload data
■
16-Byte “Buffer End Alignment”
Buffer 2:
■
10-Byte “Data Start Offset”
■
17-Bytes of payload data
■
16-Byte “Buffer End Alignment”
Figure 3.15, "TX Example 1" illustrates the TX command structure for this example, and also shows
how data is passed to the TX data FIFO.
7
Reserved.
This bit is reserved. Always write zeros to this field to guarantee future compatibility.
6:3
Collision Count.
This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
2
Excessive Deferral.
If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
1
Underrun Error.
When set, this bit indicates that the transmitter aborted the associated frame
because of an underrun condition of the TX data FIFO. TX Underrun will cause the assertion of the
TXE error flag.
0
Deferred.
When set, this bit indicates that the current packet transmission was deferred.
BITS
DESCRIPTION
相關PDF資料
PDF描述
LAN9117-MT HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9118 HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MD HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MT HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN91C100-FD-SS FEAST Fast Ethernet Controller with Full Duplex Capability
相關代理商/技術參數(shù)
參數(shù)描述
LAN9117-MT 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9118 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_05 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_07 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118-MD 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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