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參數(shù)資料
| 型號： | LAN83C185-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 45/61頁 |
| 文件大?。?/td> | 459K |
| 代理商： | LAN83C185-JT |
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
45
Rev. 0.8 (11-16-04)
DATASHEET
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the nINT interrupt if the ENERGYON interrupt is enabled. The first and possibly the second packet
to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
5.4.6
Reset
The PHY has 3 reset sources:
Hardware reset (HWRST)
: connected to the nRST input, and to the internal POR signal.
If the nRST input is driven by an external source, it should be held LOW for at least
100 us to ensure
that the Phy is properly reset.
The Phy has an internal Power-On-Reset (POR) signal which is asserted for 21ms following a VDD
(+3.3V) and VDDCORE (+1.8V) power-up. This internal POR can be bypassed only in certain
production test modes. This internal POR is internally “OR”-ed with the nRST input.
During a Hardware reset, either external or POR, an external clock
must
be supplied to the CLKIN
signal.
Software (SW) reset
: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the
register-write, internal logic extends the reset by 256μs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
Power-Down reset
: Automatically activated when the PHY comes out of power-down mode. The
internal power-down reset is extended by 256μs after exiting the power-down mode to allow the PLLs
to stabilize before the logic is released from reset.
These 3 reset sources are combined together in the digital block to create the internal “general reset”,
SYSRST, which is an asynchronous reset and is active HIGH. This SYSRST directly drives the PCS,
DSP and MII blocks. It is also input to the Central Bias block in order to generate a short reset for the
PLLs.
The SMI mechanism and registers are reset only by the Hardware and Software resets. During Power-
Down, the SMI registers are not reset. Note that some SMI register bits are not cleared by Software
reset – these are marked “NASR” in the register tables.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25
MHz if auto-negotiation is enabled.
5.4.7
LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the Phy. All LED signals are either active high or active low.
Note:
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy
address latched in on reset. The LAN83C185 senses each Phy address bit and changes the
polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will
be set to an active-low. If the address bit is set as level “0”, the LED polarity will be set to an
active-high.
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