參數(shù)資料
型號(hào)： LAN83C185-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 14/61頁(yè)
文件大?。?/td> 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Rev. 0.8 (11-16-04)
14
SMSC LAN83C185
DATASHEET
Table 3.4 Configuration Inputs
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
2
PHYAD4
I
PHY Address Bit 4:
set the
default address of the PHY.
20
PHYAD3
I
PHY Address Bit 3:
set the
default address of the PHY.
19
PHYAD2
I
PHY Address Bit 2:
set the
default address of the PHY.
17
PHYAD1
I
PHY Address Bit 1:
set the
default address of the PHY.
16
PHYAD0
I
PHY Address Bit 0:
set the
default address of the PHY.
6
MODE2
I
PHY Operating Mode Bit 2:
set the default MODE of the
PHY. See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47
for the MODE options.
5
MODE1
I
PHY Operating Mode Bit 1:
set the default MODE of the
PHY. See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47
for the MODE options.
4
MODE0
I
PHY Operating Mode Bit 0:
set the default MODE of the
PHY. See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47
for the MODE options.
10
TEST1
I
Test Mode Select 1:
Must be left floating.
9
TEST0
I
Test Mode Select 0:
Must be left floating.
12
REG_EN
I
Internal +1.8V Regulator Enable:
+3.3V – Enables internal regulator.
0V – Disables internal regulator.
Table 3.5 General Signals
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
46
nINT
OD
LAN Interrupt
– Active Low output.
25
nRST
I
External Reset
– input of the system reset. This signal is
active LOW.
23
CLKIN/XTAL1
I
Clock Input
– 25 MHz external clock or crystal input.
22
XTAL2
O
Clock Output
– 25 MHz crystal output.
11
CLK_FREQ
I
Clock Frequency
– define the frequency of the input
clock CLKIN
0 – Clock frequency is 25 MHz.
1 – Reserved.
This input needs to be held low continuously, during and
after reset. This pin should be pulled-down to VSS via a
pull-down resistor.
64
NC1
No Connect
3
GPO2
O
General Purpose Output 2 –
General Purpose Output
signal Driven by bits in registers 27 and 31.
2
GPO1
O
General Purpose Output 1 –
General Purpose Output
signal Driven by bits in registers 27 and 31.
(Muxed with PHYAD4 signal)
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