參數(shù)資料
型號(hào)： LAN83C185-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 15/61頁(yè)
文件大?。?/td> 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
15
Rev. 0.8 (11-16-04)
DATASHEET
1
GPO0
O
General Purpose Output 0 –
General Purpose Output
signal. Driven by bits in registers 27 and 31.
(Muxed with MII Select) This pin should be pulled-down
or left floating – Do Not Pull Up.
Table 3.6 10/100 Line Interface
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
51
TXP
AO
Transmit Data
: 100Base-TX or 10Base-T differential
transmit outputs to magnetics.
50
TXN
AO
Transmit Data
: 100Base-TX or 10Base-T differential
transmit outputs to magnetics.
55
RXP
AI
Receive Data
: 100Base-TX or 10Base-T differential
receive inputs from magnetics.
54
RXN
AI
Receive Data
: 100Base-TX or 10Base-T differential
receive inputs from magnetics.
Table 3.7 Analog References
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
59
EXRES1
AI
Connects to reference resistor of value 12.4K-Ohm, 1%
connected to digital GND.
Table 3.8 Analog Test Bus
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
56
NC2
AI/O
No Connect
Table 3.9 Power Signals
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
53
AVDD1
Power
+3.3V Analog Power
57
AVDD2
Power
+3.3V Analog Power
61
AVDD3
Power
+3.3V Analog Power
63
AVDD4
Power
+3.3V Analog Power
49
AVSS1
Power
Analog Ground
52
AVSS2
Power
Analog Ground
58
AVSS3
Power
Analog Ground
Table 3.5 General Signals (continued)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
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